* [PATCH, i386] PR 48743 Correctly detect AMD K6-2+ and K6-3+
@ 2011-05-16 10:37 Zuxy Meng
2011-05-16 13:27 ` H.J. Lu
0 siblings, 1 reply; 8+ messages in thread
From: Zuxy Meng @ 2011-05-16 10:37 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 484 bytes --]
Misdetected as Athlon by GCC, K6-2+ and K6-3+ are processors that support
extended 3DNow! but don't support extended MMX or CMOV.
I don't own a K6-2 or Athlon machine. Can anybody have the patch tested?
2011-05-16 Zuxy Meng <zuxy.meng@gmail.com>
PR i386/48743
* config/i386/cpuid.h (bit_MMXEXT): New
* config/i386/cpuid.h (bit_3DNOWP): Deleted
* config/i386/driver-i386.c (host_detect_local_cpu): Detect Athlon by the
presence of extended MMX instead of extended 3DNow!
--
Zuxy
[-- Attachment #2: k6-3+.diff --]
[-- Type: application/octet-stream, Size: 1345 bytes --]
--- cpuid.h.orig 2011-05-12 16:15:00 +0800
+++ cpuid.h 2011-05-12 16:17:22 +0800
@@ -57,8 +57,8 @@
#define bit_TBM (1 << 21)
/* %edx */
+#define bit_MMXEXT (1 << 22)
#define bit_LM (1 << 29)
-#define bit_3DNOWP (1 << 30)
#define bit_3DNOW (1 << 31)
/* Extended Features (%eax == 7) */
--- driver-i386.c.orig 2011-05-12 16:13:47 +0800
+++ driver-i386.c 2011-05-12 16:21:39 +0800
@@ -391,7 +391,7 @@
/* Extended features */
unsigned int has_lahf_lm = 0, has_sse4a = 0;
- unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
+ unsigned int has_mmxext = 0, has_longmode = 0, has_3dnow = 0;
unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0;
unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
@@ -465,8 +465,8 @@
has_xop = ecx & bit_XOP;
has_tbm = ecx & bit_TBM;
+ has_mmxext = edx & bit_MMXEXT;
has_longmode = edx & bit_LM;
- has_3dnowp = edx & bit_3DNOWP;
has_3dnow = edx & bit_3DNOW;
__cpuid (0x7, eax, ebx, ecx, edx);
@@ -506,7 +506,7 @@
processor = PROCESSOR_AMDFAM10;
else if (has_sse2 || has_longmode)
processor = PROCESSOR_K8;
- else if (has_3dnowp)
+ else if (has_mmxext)
processor = PROCESSOR_ATHLON;
else if (has_mmx)
processor = PROCESSOR_K6;
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH, i386] PR 48743 Correctly detect AMD K6-2+ and K6-3+
2011-05-16 10:37 [PATCH, i386] PR 48743 Correctly detect AMD K6-2+ and K6-3+ Zuxy Meng
@ 2011-05-16 13:27 ` H.J. Lu
2011-05-17 7:15 ` Zuxy Meng
0 siblings, 1 reply; 8+ messages in thread
From: H.J. Lu @ 2011-05-16 13:27 UTC (permalink / raw)
To: Zuxy Meng; +Cc: gcc-patches
On Sun, May 15, 2011 at 10:03 PM, Zuxy Meng <zuxy.meng@gmail.com> wrote:
> Misdetected as Athlon by GCC, K6-2+ and K6-3+ are processors that support
> extended 3DNow! but don't support extended MMX or CMOV.
>
> I don't own a K6-2 or Athlon machine. Can anybody have the patch tested?
>
> 2011-05-16 Zuxy Meng <zuxy.meng@gmail.com>
> PR i386/48743
> * config/i386/cpuid.h (bit_MMXEXT): New
> * config/i386/cpuid.h (bit_3DNOWP): Deleted
Why do you remove bit_3DNOWP? <cpuid.h> is a public header file.
--
H.J.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, i386] PR 48743 Correctly detect AMD K6-2+ and K6-3+
2011-05-16 13:27 ` H.J. Lu
@ 2011-05-17 7:15 ` Zuxy Meng
2011-05-17 7:15 ` H.J. Lu
0 siblings, 1 reply; 8+ messages in thread
From: Zuxy Meng @ 2011-05-17 7:15 UTC (permalink / raw)
To: H.J. Lu; +Cc: gcc-patches
2011/5/16 H.J. Lu <hjl.tools@gmail.com>:
> On Sun, May 15, 2011 at 10:03 PM, Zuxy Meng <zuxy.meng@gmail.com> wrote:
>> Misdetected as Athlon by GCC, K6-2+ and K6-3+ are processors that support
>> extended 3DNow! but don't support extended MMX or CMOV.
>>
>> I don't own a K6-2 or Athlon machine. Can anybody have the patch tested?
>>
>> 2011-05-16 Zuxy Meng <zuxy.meng@gmail.com>
>> PR i386/48743
>> * config/i386/cpuid.h (bit_MMXEXT): New
>> * config/i386/cpuid.h (bit_3DNOWP): Deleted
>
> Why do you remove bit_3DNOWP? <cpuid.h> is a public header file.
Because this bit was added to detect Athlon and not used elsewhere.
cpuid.h doesn't define all the feature bits available in the output of
CPUID instruction so I thought only the actually used bits are to be
included.
--
Zuxy
Beauty is truth,
While truth is beauty.
PGP KeyID: E8555ED6
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, i386] PR 48743 Correctly detect AMD K6-2+ and K6-3+
2011-05-17 7:15 ` Zuxy Meng
@ 2011-05-17 7:15 ` H.J. Lu
2011-05-17 7:16 ` Zuxy Meng
0 siblings, 1 reply; 8+ messages in thread
From: H.J. Lu @ 2011-05-17 7:15 UTC (permalink / raw)
To: Zuxy Meng; +Cc: gcc-patches
On Mon, May 16, 2011 at 7:41 PM, Zuxy Meng <zuxy.meng@gmail.com> wrote:
> 2011/5/16 H.J. Lu <hjl.tools@gmail.com>:
>> On Sun, May 15, 2011 at 10:03 PM, Zuxy Meng <zuxy.meng@gmail.com> wrote:
>>> Misdetected as Athlon by GCC, K6-2+ and K6-3+ are processors that support
>>> extended 3DNow! but don't support extended MMX or CMOV.
>>>
>>> I don't own a K6-2 or Athlon machine. Can anybody have the patch tested?
>>>
>>> 2011-05-16 Zuxy Meng <zuxy.meng@gmail.com>
>>> PR i386/48743
>>> * config/i386/cpuid.h (bit_MMXEXT): New
>>> * config/i386/cpuid.h (bit_3DNOWP): Deleted
>>
>> Why do you remove bit_3DNOWP? <cpuid.h> is a public header file.
>
> Because this bit was added to detect Athlon and not used elsewhere.
The first part might be true and the second part is false. Since
<cpuid.h> is a public header file, it may be used in any software
packages.
> cpuid.h doesn't define all the feature bits available in the output of
> CPUID instruction so I thought only the actually used bits are to be
> included.
That is false. I would appreciate a patch to define all feature bits.
--
H.J.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, i386] PR 48743 Correctly detect AMD K6-2+ and K6-3+
2011-05-17 7:15 ` H.J. Lu
@ 2011-05-17 7:16 ` Zuxy Meng
0 siblings, 0 replies; 8+ messages in thread
From: Zuxy Meng @ 2011-05-17 7:16 UTC (permalink / raw)
To: H.J. Lu; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1514 bytes --]
2011/5/17 H.J. Lu <hjl.tools@gmail.com>:
> On Mon, May 16, 2011 at 7:41 PM, Zuxy Meng <zuxy.meng@gmail.com> wrote:
>> 2011/5/16 H.J. Lu <hjl.tools@gmail.com>:
>>> On Sun, May 15, 2011 at 10:03 PM, Zuxy Meng <zuxy.meng@gmail.com> wrote:
>>>> Misdetected as Athlon by GCC, K6-2+ and K6-3+ are processors that support
>>>> extended 3DNow! but don't support extended MMX or CMOV.
>>>>
>>>> I don't own a K6-2 or Athlon machine. Can anybody have the patch tested?
>>>>
>>>> 2011-05-16 Zuxy Meng <zuxy.meng@gmail.com>
>>>> PR i386/48743
>>>> * config/i386/cpuid.h (bit_MMXEXT): New
>>>> * config/i386/cpuid.h (bit_3DNOWP): Deleted
>>>
>>> Why do you remove bit_3DNOWP? <cpuid.h> is a public header file.
>>
>> Because this bit was added to detect Athlon and not used elsewhere.
>
> The first part might be true and the second part is false. Since
> <cpuid.h> is a public header file, it may be used in any software
> packages.
>
>> cpuid.h doesn't define all the feature bits available in the output of
>> CPUID instruction so I thought only the actually used bits are to be
>> included.
>
> That is false. I would appreciate a patch to define all feature bits.
OK. Resending patch.
2011-05-16 Zuxy Meng <zuxy.meng@gmail.com>
PR i386/48743
* config/i386/cpuid.h (bit_MMXEXT): New
* config/i386/driver-i386.c (host_detect_local_cpu): Detect Athlon by
the presence of extended MMX instead of extended 3DNow!
--
Zuxy
Beauty is truth,
While truth is beauty.
PGP KeyID: E8555ED6
[-- Attachment #2: k6-3+.diff --]
[-- Type: application/octet-stream, Size: 1346 bytes --]
--- cpuid.h.orig 2010-11-11 06:02:34 +0800
+++ cpuid.h 2011-05-17 11:08:14 +0800
@@ -57,6 +57,7 @@
#define bit_TBM (1 << 21)
/* %edx */
+#define bit_MMXEXT (1 << 22)
#define bit_LM (1 << 29)
#define bit_3DNOWP (1 << 30)
#define bit_3DNOW (1 << 31)
--- driver-i386.c.orig 2011-05-12 16:13:47 +0800
+++ driver-i386.c 2011-05-12 16:21:39 +0800
@@ -391,7 +391,7 @@
/* Extended features */
unsigned int has_lahf_lm = 0, has_sse4a = 0;
- unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
+ unsigned int has_mmxext = 0, has_longmode = 0, has_3dnow = 0;
unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0;
unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
@@ -465,8 +465,8 @@
has_xop = ecx & bit_XOP;
has_tbm = ecx & bit_TBM;
+ has_mmxext = edx & bit_MMXEXT;
has_longmode = edx & bit_LM;
- has_3dnowp = edx & bit_3DNOWP;
has_3dnow = edx & bit_3DNOW;
__cpuid (0x7, eax, ebx, ecx, edx);
@@ -506,7 +506,7 @@
processor = PROCESSOR_AMDFAM10;
else if (has_sse2 || has_longmode)
processor = PROCESSOR_K8;
- else if (has_3dnowp)
+ else if (has_mmxext)
processor = PROCESSOR_ATHLON;
else if (has_mmx)
processor = PROCESSOR_K6;
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, i386] PR 48743 Correctly detect AMD K6-2+ and K6-3+
@ 2011-05-18 12:34 Uros Bizjak
2011-05-20 10:10 ` Zuxy Meng
0 siblings, 1 reply; 8+ messages in thread
From: Uros Bizjak @ 2011-05-18 12:34 UTC (permalink / raw)
To: gcc-patches; +Cc: Zuxy Meng, H.J. Lu, Jagasia, Harsha
Hello!
> 2011-05-16 Zuxy Meng <zuxy.meng@gmail.com>
> PR i386/48743
> * config/i386/cpuid.h (bit_MMXEXT): New
> * config/i386/driver-i386.c (host_detect_local_cpu): Detect Athlon by
> the presence of extended MMX instead of extended 3DNow!
PR target/48743
The patch is OK, but please also get a confirmation from someone from
AMD (CC'd).
Thanks,
Uros.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, i386] PR 48743 Correctly detect AMD K6-2+ and K6-3+
2011-05-18 12:34 Uros Bizjak
@ 2011-05-20 10:10 ` Zuxy Meng
2011-05-20 15:53 ` Jagasia, Harsha
0 siblings, 1 reply; 8+ messages in thread
From: Zuxy Meng @ 2011-05-20 10:10 UTC (permalink / raw)
To: Uros Bizjak; +Cc: gcc-patches, H.J. Lu, Jagasia, Harsha
2011/5/18 Uros Bizjak <ubizjak@gmail.com>:
> Hello!
>
>> 2011-05-16 Zuxy Meng <zuxy.meng@gmail.com>
>
>> PR i386/48743
>> * config/i386/cpuid.h (bit_MMXEXT): New
>> * config/i386/driver-i386.c (host_detect_local_cpu): Detect Athlon by
>> the presence of extended MMX instead of extended 3DNow!
>
> PR target/48743
>
> The patch is OK, but please also get a confirmation from someone from
> AMD (CC'd).
>
Any update?
--
Zuxy
Beauty is truth,
While truth is beauty.
PGP KeyID: E8555ED6
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH, i386] PR 48743 Correctly detect AMD K6-2+ and K6-3+
2011-05-20 10:10 ` Zuxy Meng
@ 2011-05-20 15:53 ` Jagasia, Harsha
0 siblings, 0 replies; 8+ messages in thread
From: Jagasia, Harsha @ 2011-05-20 15:53 UTC (permalink / raw)
To: 'Zuxy Meng', 'Uros Bizjak'
Cc: 'gcc-patches@gcc.gnu.org', 'H.J. Lu'
I am still waiting for someone in AMD to confirm/looking at some docs that can confirm.
I will get back once I have the info.
Thanks,
Harsha
> -----Original Message-----
> From: Zuxy Meng [mailto:zuxy.meng@gmail.com]
> Sent: Friday, May 20, 2011 2:36 AM
> To: Uros Bizjak
> Cc: gcc-patches@gcc.gnu.org; H.J. Lu; Jagasia, Harsha
> Subject: Re: [PATCH, i386] PR 48743 Correctly detect AMD K6-2+ and K6-
> 3+
>
> 2011/5/18 Uros Bizjak <ubizjak@gmail.com>:
> > Hello!
> >
> >> 2011-05-16 Zuxy Meng <zuxy.meng@gmail.com>
> >
> >> PR i386/48743
> >> * config/i386/cpuid.h (bit_MMXEXT): New
> >> * config/i386/driver-i386.c (host_detect_local_cpu): Detect Athlon
> by
> >> the presence of extended MMX instead of extended 3DNow!
> >
> > PR target/48743
> >
> > The patch is OK, but please also get a confirmation from someone from
> > AMD (CC'd).
> >
>
> Any update?
>
> --
> Zuxy
> Beauty is truth,
> While truth is beauty.
> PGP KeyID: E8555ED6
^ permalink raw reply [flat|nested] 8+ messages in thread
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2011-05-16 10:37 [PATCH, i386] PR 48743 Correctly detect AMD K6-2+ and K6-3+ Zuxy Meng
2011-05-16 13:27 ` H.J. Lu
2011-05-17 7:15 ` Zuxy Meng
2011-05-17 7:15 ` H.J. Lu
2011-05-17 7:16 ` Zuxy Meng
2011-05-18 12:34 Uros Bizjak
2011-05-20 10:10 ` Zuxy Meng
2011-05-20 15:53 ` Jagasia, Harsha
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