From: Uros Bizjak <ubizjak@gmail.com>
To: gcc-patches@gcc.gnu.org
Subject: [PATCH 5/n, i386]: Merge SSE and AVX patterns using "enable" attribute.
Date: Mon, 11 Apr 2011 20:54:00 -0000 [thread overview]
Message-ID: <BANLkTinKh=1+xdci1PNPktJ9c=PJObx1JA@mail.gmail.com> (raw)
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Hello!
Attached patch merges "Parallel bitwise logical operations" section of
sse.md. In addition to the merge, the patch also enables these
patterns for TARGET_SSE (using PS version of the insn) and handles
TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL target flag.
2011-04-12 Uros Bizjak <ubizjak@gmail.com>
* config/i386/sse.md (VI): New mode iterator.
(SSEMODEI): Remove.
(AVX256MODEI): Ditto.
(AVXMODEF4P): Ditto.
(avxvecpsmode): Ditto.
(one_cmpl<mode>2): Enable for TARGET_SSE. Use VI mode iterator.
(sse2_andnot<mode>3): New expander.
(*andnot<mode>3): Merge with *sse2_andnot<mode>3 and
*avx_andnot<mode>3. Enable for TARGET_SSE. Use VI mode iterator.
Handle TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL target flag.
(<any_logic:code><mode>3): Use VI mode iterator.
(*<any_logic:code><mode>3): Merge with *sse2_<any_logic:code><mode>3
and *avx_<any_logic:code><mode>3. Enable for TARGET_SSE. Use VI mode
iterator. Handle TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL target flag.
(*andnottf3): Handle AVX three-operand constraints. Enable for
TARGET_SSE. Handle TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL target flag.
(<any_logic:code>tf3): Enable for TARGET_SSE.
(*<any_logic:code>tf3): Handle AVX three-operand constraints.
Enable for TARGET_SSE. Handle TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
target flag.
Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu
{,-m32} AVX target.
Patch was committed to mainline SVN.
Uros.
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Index: sse.md
===================================================================
--- sse.md (revision 172266)
+++ sse.md (working copy)
@@ -36,6 +36,13 @@
(define_mode_iterator VF_128
[(V4SF "TARGET_SSE") (V2DF "TARGET_SSE2")])
+;; All vector integer modes
+(define_mode_iterator VI
+ [(V32QI "TARGET_AVX") V16QI
+ (V16HI "TARGET_AVX") V8HI
+ (V8SI "TARGET_AVX") V4SI
+ (V4DI "TARGET_AVX") V2DI])
+
;; All 128bit vector integer modes
(define_mode_iterator VI_128 [V16QI V8HI V4SI V2DI])
@@ -50,16 +57,10 @@
;; Instruction suffix for sign and zero extensions.
(define_code_attr extsuffix [(sign_extend "sx") (zero_extend "zx")])
-;; 16 byte integral modes handled by SSE
-(define_mode_iterator SSEMODEI [V16QI V8HI V4SI V2DI])
-
;; All 16-byte vector modes handled by SSE
(define_mode_iterator SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF])
(define_mode_iterator SSEMODE16 [V16QI V8HI V4SI V2DI V1TI V4SF V2DF])
-;; 32 byte integral vector modes handled by AVX
-(define_mode_iterator AVX256MODEI [V32QI V16HI V8SI V4DI])
-
;; All 32-byte vector modes handled by AVX
(define_mode_iterator AVX256MODE [V32QI V16HI V8SI V4DI V8SF V4DF])
@@ -86,7 +87,6 @@
(define_mode_iterator AVX256MODE4P [V4DI V4DF])
(define_mode_iterator AVX256MODE8P [V8SI V8SF])
(define_mode_iterator AVXMODEF2P [V4SF V2DF V8SF V4DF])
-(define_mode_iterator AVXMODEF4P [V4SF V4DF])
(define_mode_iterator AVXMODEFDP [V2DF V4DF])
(define_mode_iterator AVXMODEFSP [V4SF V8SF])
@@ -160,9 +160,6 @@
[(V16QI "TI") (V8HI "TI") (V4SI "TI") (V2DI "TI") (V1TI "TI")
(V4SF "V4SF") (V8SF "V8SF") (V2DF "V2DF") (V4DF "V4DF")
(V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI")])
-(define_mode_attr avxvecpsmode
- [(V16QI "V4SF") (V8HI "V4SF") (V4SI "V4SF") (V2DI "V4SF")
- (V32QI "V8SF") (V16HI "V8SF") (V8SI "V8SF") (V4DI "V8SF")])
(define_mode_attr avxhalfvecmode
[(V32QI "V16QI") (V16HI "V8HI") (V8SI "V4SI") (V4DI "V2DI")
(V8SF "V4SF") (V4DF "V2DF")
@@ -5775,10 +5772,10 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "one_cmpl<mode>2"
- [(set (match_operand:SSEMODEI 0 "register_operand" "")
- (xor:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
- (match_dup 2)))]
- "TARGET_SSE2"
+ [(set (match_operand:VI 0 "register_operand" "")
+ (xor:VI (match_operand:VI 1 "nonimmediate_operand" "")
+ (match_dup 2)))]
+ "TARGET_SSE"
{
int i, n = GET_MODE_NUNITS (<MODE>mode);
rtvec v = rtvec_alloc (n);
@@ -5789,133 +5786,215 @@
operands[2] = force_reg (<MODE>mode, gen_rtx_CONST_VECTOR (<MODE>mode, v));
})
-(define_insn "*avx_andnot<mode>3"
- [(set (match_operand:AVX256MODEI 0 "register_operand" "=x")
- (and:AVX256MODEI
- (not:AVX256MODEI (match_operand:AVX256MODEI 1 "register_operand" "x"))
- (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX"
- "vandnps\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecpsmode>")])
+(define_expand "sse2_andnot<mode>3"
+ [(set (match_operand:VI_128 0 "register_operand" "")
+ (and:VI_128
+ (not:VI_128 (match_operand:VI_128 1 "register_operand" ""))
+ (match_operand:VI_128 2 "nonimmediate_operand" "")))]
+ "TARGET_SSE2")
-(define_insn "*sse_andnot<mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (and:SSEMODEI
- (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0"))
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "(TARGET_SSE && !TARGET_SSE2)"
- "andnps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V4SF")])
+(define_insn "*andnot<mode>3"
+ [(set (match_operand:VI 0 "register_operand" "=x,x")
+ (and:VI
+ (not:VI (match_operand:VI 1 "register_operand" "0,x"))
+ (match_operand:VI 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE"
+{
+ static char buf[32];
+ const char *ops;
+ const char *tmp
+ = (get_attr_mode (insn) == MODE_TI) ? "pandn" : "andnps";
-(define_insn "*avx_andnot<mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (and:SSEMODEI
- (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "x"))
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX"
- "vpandn\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
+ switch (which_alternative)
+ {
+ case 0:
+ ops = "%s\t{%%2, %%0|%%0, %%2}";
+ break;
+ case 1:
+ ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ break;
+ default:
+ gcc_unreachable ();
+ }
-(define_insn "sse2_andnot<mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (and:SSEMODEI
- (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0"))
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pandn\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
+ snprintf (buf, sizeof (buf), ops, tmp);
+ return buf;
+}
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (and (eq_attr "alternative" "0")
+ (eq_attr "mode" "TI"))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "prefix" "orig,vex")
+ (set (attr "mode")
+ (cond [(ne (symbol_ref "GET_MODE_SIZE (<MODE>mode) > 128") (const_int 0))
+ (const_string "V8SF")
+ (ne (symbol_ref "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_int 0))
+ (const_string "V4SF")
+ (ne (symbol_ref "TARGET_SSE2") (const_int 0))
+ (const_string "TI")
+ ]
+ (const_string "V4SF")))])
-(define_insn "*andnottf3"
- [(set (match_operand:TF 0 "register_operand" "=x")
- (and:TF
- (not:TF (match_operand:TF 1 "register_operand" "0"))
- (match_operand:TF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pandn\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
(define_expand "<code><mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "")
- (any_logic:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:VI 0 "register_operand" "")
+ (any_logic:VI
+ (match_operand:VI 1 "nonimmediate_operand" "")
+ (match_operand:VI 2 "nonimmediate_operand" "")))]
"TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
-(define_insn "*avx_<code><mode>3"
- [(set (match_operand:AVX256MODEI 0 "register_operand" "=x")
- (any_logic:AVX256MODEI
- (match_operand:AVX256MODEI 1 "nonimmediate_operand" "%x")
- (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX
+(define_insn "*<code><mode>3"
+ [(set (match_operand:VI 0 "register_operand" "=x,x")
+ (any_logic:VI
+ (match_operand:VI 1 "nonimmediate_operand" "%0,x")
+ (match_operand:VI 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecpsmode>")])
+{
+ static char buf[32];
+ const char *ops;
+ const char *tmp
+ = (get_attr_mode (insn) == MODE_TI) ? "p<logic>" : "<logic>ps";
-(define_insn "*sse_<code><mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (any_logic:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "(TARGET_SSE && !TARGET_SSE2)
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<logic>ps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V4SF")])
+ switch (which_alternative)
+ {
+ case 0:
+ ops = "%s\t{%%2, %%0|%%0, %%2}";
+ break;
+ case 1:
+ ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ break;
+ default:
+ gcc_unreachable ();
+ }
-(define_insn "*avx_<code><mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (any_logic:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "%x")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "vp<logic>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
+ snprintf (buf, sizeof (buf), ops, tmp);
+ return buf;
+}
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (and (eq_attr "alternative" "0")
+ (eq_attr "mode" "TI"))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "prefix" "orig,vex")
+ (set (attr "mode")
+ (cond [(ne (symbol_ref "GET_MODE_SIZE (<MODE>mode) > 128") (const_int 0))
+ (const_string "V8SF")
+ (ne (symbol_ref "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_int 0))
+ (const_string "V4SF")
+ (ne (symbol_ref "TARGET_SSE2") (const_int 0))
+ (const_string "TI")
+ ]
+ (const_string "V4SF")))])
-(define_insn "*sse2_<code><mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (any_logic:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "p<logic>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
+(define_insn "*andnottf3"
+ [(set (match_operand:TF 0 "register_operand" "=x,x")
+ (and:TF
+ (not:TF (match_operand:TF 1 "register_operand" "0,x"))
+ (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE"
+{
+ static char buf[32];
+ const char *ops;
+ const char *tmp
+ = (get_attr_mode (insn) == MODE_TI) ? "pandn" : "andnps";
+ switch (which_alternative)
+ {
+ case 0:
+ ops = "%s\t{%%2, %%0|%%0, %%2}";
+ break;
+ case 1:
+ ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ snprintf (buf, sizeof (buf), ops, tmp);
+ return buf;
+}
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (and (eq_attr "alternative" "0")
+ (eq_attr "mode" "TI"))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "prefix" "orig,vex")
+ (set (attr "mode")
+ (cond [(ne (symbol_ref "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_int 0))
+ (const_string "V4SF")
+ (ne (symbol_ref "TARGET_SSE2") (const_int 0))
+ (const_string "TI")
+ ]
+ (const_string "V4SF")))])
+
(define_expand "<code>tf3"
[(set (match_operand:TF 0 "register_operand" "")
(any_logic:TF
(match_operand:TF 1 "nonimmediate_operand" "")
(match_operand:TF 2 "nonimmediate_operand" "")))]
- "TARGET_SSE2"
+ "TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);")
(define_insn "*<code>tf3"
- [(set (match_operand:TF 0 "register_operand" "=x")
+ [(set (match_operand:TF 0 "register_operand" "=x,x")
(any_logic:TF
- (match_operand:TF 1 "nonimmediate_operand" "%0")
- (match_operand:TF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
- "p<logic>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
+ (match_operand:TF 1 "nonimmediate_operand" "%0,x")
+ (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE
+ && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
+{
+ static char buf[32];
+ const char *ops;
+ const char *tmp
+ = (get_attr_mode (insn) == MODE_TI) ? "p<logic>" : "<logic>ps";
+ switch (which_alternative)
+ {
+ case 0:
+ ops = "%s\t{%%2, %%0|%%0, %%2}";
+ break;
+ case 1:
+ ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ snprintf (buf, sizeof (buf), ops, tmp);
+ return buf;
+}
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (and (eq_attr "alternative" "0")
+ (eq_attr "mode" "TI"))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "prefix" "orig,vex")
+ (set (attr "mode")
+ (cond [(ne (symbol_ref "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_int 0))
+ (const_string "V4SF")
+ (ne (symbol_ref "TARGET_SSE2") (const_int 0))
+ (const_string "TI")
+ ]
+ (const_string "V4SF")))])
+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Parallel integral element swizzling
next reply other threads:[~2011-04-11 20:54 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-11 20:54 Uros Bizjak [this message]
2011-04-11 21:30 ` Uros Bizjak
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