From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 2386 invoked by alias); 23 Jun 2011 05:40:23 -0000 Received: (qmail 2378 invoked by uid 22791); 23 Jun 2011 05:40:22 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,RFC_ABUSE_POST X-Spam-Check-By: sourceware.org Received: from mail-qw0-f47.google.com (HELO mail-qw0-f47.google.com) (209.85.216.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 23 Jun 2011 05:40:07 +0000 Received: by qwh5 with SMTP id 5so841638qwh.20 for ; Wed, 22 Jun 2011 22:40:07 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.106.34 with SMTP id v34mr1241994qco.111.1308807605410; Wed, 22 Jun 2011 22:40:05 -0700 (PDT) Received: by 10.229.47.78 with HTTP; Wed, 22 Jun 2011 22:40:05 -0700 (PDT) In-Reply-To: <4DFFA1AE.7070405@codesourcery.com> References: <4DF9FA9A.8040505@codesourcery.com> <4DFA2E85.2030601@redhat.com> <4DFFA1AE.7070405@codesourcery.com> Date: Thu, 23 Jun 2011 06:23:00 -0000 Message-ID: Subject: Re: Add __builtin_clrsb, similar to clz/ctz From: "H.J. Lu" To: Bernd Schmidt Cc: Richard Henderson , GCC Patches Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-06/txt/msg01739.txt.bz2 On Mon, Jun 20, 2011 at 12:38 PM, Bernd Schmidt w= rote: > On 06/16/2011 06:25 PM, Richard Henderson wrote: >> On 06/16/2011 05:44 AM, Bernd Schmidt wrote: >>> +@deftypefn {Built-in Function} int __builtin_clrsb (unsigned int x) >>> +Returns the number of leading redundant sign bits in @var{x}, starting >>> +at the most significant bit position. >>> +@end deftypefn >> >> Do we want a signed argument, since we're talking about signs? > > Err, yes. It's signed everywhere else (builtins.def etc.). > >> It would seem that unlike clz, this function is not undefined for zero. >> What about INT_MIN? =A0Do all cpus handle those edge cases the same way? > > -1 and zero should both produce the same value, 31 (for a 32 bit > integer). I don't see why INT_MIN should be special - the return value > is zero. This is true for C6X and Blackfin; ARM documentation suggests > it's also true for their VCLS instruction. I've not found proper > picochip documentation but some other documents that suggest it's also > implemented this way. > >> Do you get smaller code in general from >> >> =A0 if (x < 0) >> =A0 =A0 x =3D ~x; >> =A0 if (x =3D=3D 0) >> =A0 =A0 return W_TYPE_SIZE - 1; >> =A0 count_leading_zeros(ret, x); >> =A0 return ret - 1; > > Probably. > >>> -(define_insn "signbitssi2" >>> +(define_insn "clrsbsi2" >>> =A0 =A0[(set (match_operand:HI 0 "register_operand" "=3Dd") >>> =A0 =A0 =A0(if_then_else:HI >>> =A0 =A0 =A0 (lt (match_operand:SI 1 "register_operand" "d") (const_int = 0)) >> >> No use of the new rtx code? > > D'oh. Blackfin has a (clrsb:HI (operand:SI)) instruction, so adding this > showed a problem with some of the existing simplify_const_unop cases: > for ffs/clz/ctz/clrsb/parity/popcount, we should look at the mode of the > operand, rather than the mode of the operation. This limits what we can > do in that function, since op_mode is sometimes VOIDmode - we really > should add builtin folders for these at some point. > > New patch below. Retested on i686 and bfin. This caused: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D49512 --=20 H.J.