From: "Kong, Lingling" <lingling.kong@intel.com>
To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: "Liu, Hongtao" <hongtao.liu@intel.com>,
Uros Bizjak <ubizjak@gmail.com>,
"Kong, Lingling" <lingling.kong@intel.com>
Subject: [PATCH v2 4/8] [APX NF] Support APX NF for right shift insns
Date: Wed, 22 May 2024 08:41:56 +0000 [thread overview]
Message-ID: <BN9PR11MB5483ED4DE65AECCB9C18433BECEB2@BN9PR11MB5483.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20240522073710.2039035-4-lingling.kong@intel.com>
gcc/ChangeLog:
* config/i386/i386.md (*ashr<mode>3_1_nf): New.
(*lshr<mode>3_1_nf): Ditto.
(*lshrqi3_1_nf): Ditto.
(*lshrhi3_1_nf): Ditto.
---
gcc/config/i386/i386.md | 82 +++++++++++++++++++++++------------------
1 file changed, 46 insertions(+), 36 deletions(-)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 271d449d7c4..7f191749342 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -16308,13 +16308,13 @@
[(set_attr "type" "ishiftx")
(set_attr "mode" "<MODE>")])
-(define_insn "*ashr<mode>3_1"
+(define_insn "*ashr<mode>3_1<nf_name>"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r")
(ashiftrt:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "0,rm,rm")
- (match_operand:QI 2 "nonmemory_operand" "c<S>,r,c<S>")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)"
+ (match_operand:QI 2 "nonmemory_operand" "c<S>,r,c<S>")))]
+ "ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)
+ && <nf_condition>"
{
bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
switch (get_attr_type (insn))
@@ -16325,11 +16325,11 @@
default:
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && !use_ndd)
+ && !use_ndd && !<nf_applied>)
return "sar{<imodesuffix>}\t%0";
else
- return use_ndd ? "sar{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
- : "sar{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return use_ndd ? "<nf_prefix>sar{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ : "<nf_prefix>sar{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set_attr "isa" "*,bmi2,apx_ndd")
@@ -16369,14 +16369,13 @@
}
[(set_attr "isa" "*,*,*,apx_ndd")])
-
-(define_insn "*lshr<mode>3_1"
+(define_insn "*lshr<mode>3_1<nf_name>"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,?k,r")
(lshiftrt:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "0,rm,k,rm")
- (match_operand:QI 2 "nonmemory_operand" "c<S>,r,<KS>,c<S>")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (LSHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)"
+ (match_operand:QI 2 "nonmemory_operand" "c<S>,r,<KS>,c<S>")))]
+ "ix86_binary_operator_ok (LSHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)
+ && <nf_condition>"
{
bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
switch (get_attr_type (insn))
@@ -16388,11 +16387,11 @@
default:
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && !use_ndd)
+ && !use_ndd && !<nf_applied>)
return "shr{<imodesuffix>}\t%0";
else
- return use_ndd ? "shr{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
- : "shr{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return use_ndd ? "<nf_prefix>shr{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ : "<nf_prefix>shr{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set_attr "isa" "*,bmi2,avx512bw,apx_ndd") @@ -16408,6 +16407,17 @@
(set_attr "mode" "<MODE>")])
;; Convert shift to the shiftx pattern to avoid flags dependency.
+;; For NF/NDD doesn't support shift count as r, it just support c<S>,
+;; but it has no flag.
+(define_split
+ [(set (match_operand:SWI48 0 "register_operand")
+ (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:QI 2 "register_operand")))]
+ "TARGET_BMI2 && reload_completed"
+ [(set (match_dup 0)
+ (any_shiftrt:SWI48 (match_dup 1) (match_dup 2)))]
+ "operands[2] = gen_lowpart (<MODE>mode, operands[2]);")
+
(define_split
[(set (match_operand:SWI48 0 "register_operand")
(any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") @@ -16476,22 +16486,22 @@
(zero_extend:DI (any_shiftrt:SI (match_dup 1) (match_dup 2))))]
"operands[2] = gen_lowpart (SImode, operands[2]);")
-(define_insn "*ashr<mode>3_1"
+(define_insn "*ashr<mode>3_1<nf_name>"
[(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m, r")
(ashiftrt:SWI12
(match_operand:SWI12 1 "nonimmediate_operand" "0, rm")
- (match_operand:QI 2 "nonmemory_operand" "c<S>, c<S>")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)"
+ (match_operand:QI 2 "nonmemory_operand" "c<S>, c<S>")))]
+ "ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)
+ && <nf_condition>"
{
bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && !use_ndd)
+ && !use_ndd && !<nf_applied>)
return "sar{<imodesuffix>}\t%0";
else
- return use_ndd ? "sar{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
- : "sar{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return use_ndd ? "<nf_prefix>sar{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ : "<nf_prefix>sar{<imodesuffix>}\t{%2, %0|%0, %2}";
}
[(set_attr "isa" "*, apx_ndd")
(set_attr "type" "ishift")
@@ -16504,13 +16514,13 @@
(const_string "*")))
(set_attr "mode" "<MODE>")])
-(define_insn "*lshrqi3_1"
+(define_insn "*lshrqi3_1<nf_name>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?k,r")
(lshiftrt:QI
(match_operand:QI 1 "nonimmediate_operand" "0, k, rm")
- (match_operand:QI 2 "nonmemory_operand" "cI,Wb,cI")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (LSHIFTRT, QImode, operands, TARGET_APX_NDD)"
+ (match_operand:QI 2 "nonmemory_operand" "cI,Wb,cI")))]
+ "ix86_binary_operator_ok (LSHIFTRT, QImode, operands, TARGET_APX_NDD)
+ && <nf_condition>"
{
bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
switch (get_attr_type (insn))
@@ -16518,11 +16528,11 @@
case TYPE_ISHIFT:
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && !use_ndd)
+ && !use_ndd && !<nf_applied>)
return "shr{b}\t%0";
else
- return use_ndd ? "shr{b}\t{%2, %1, %0|%0, %1, %2}"
- : "shr{b}\t{%2, %0|%0, %2}";
+ return use_ndd ? "<nf_prefix>shr{b}\t{%2, %1, %0|%0, %1, %2}"
+ : "<nf_prefix>shr{b}\t{%2, %0|%0, %2}";
case TYPE_MSKLOG:
return "#";
default:
@@ -16541,13 +16551,13 @@
(const_string "*")))
(set_attr "mode" "QI")])
-(define_insn "*lshrhi3_1"
+(define_insn "*lshrhi3_1<nf_name>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm, ?k, r")
(lshiftrt:HI
(match_operand:HI 1 "nonimmediate_operand" "0, k, rm")
- (match_operand:QI 2 "nonmemory_operand" "cI, Ww, cI")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (LSHIFTRT, HImode, operands, TARGET_APX_NDD)"
+ (match_operand:QI 2 "nonmemory_operand" "cI, Ww, cI")))]
+ "ix86_binary_operator_ok (LSHIFTRT, HImode, operands, TARGET_APX_NDD)
+ && <nf_condition>"
{
bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
switch (get_attr_type (insn))
@@ -16555,11 +16565,11 @@
case TYPE_ISHIFT:
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && !use_ndd)
+ && !use_ndd && !<nf_applied>)
return "shr{w}\t%0";
else
- return use_ndd ? "shr{w}\t{%2, %1, %0|%0, %1, %2}"
- : "shr{w}\t{%2, %0|%0, %2}";
+ return use_ndd ? "<nf_prefix>shr{w}\t{%2, %1, %0|%0, %1, %2}"
+ : "<nf_prefix>shr{w}\t{%2, %0|%0, %2}";
case TYPE_MSKLOG:
return "#";
default:
--
2.31.1
next prev parent reply other threads:[~2024-05-22 8:42 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20240522073710.2039035-1-lingling.kong@intel.com>
[not found] ` <20240522073710.2039035-3-lingling.kong@intel.com>
2024-05-22 8:41 ` [PATCH v2 3/8] [APX NF] Support APX NF for left " Kong, Lingling
[not found] ` <20240522073710.2039035-4-lingling.kong@intel.com>
2024-05-22 8:41 ` Kong, Lingling [this message]
[not found] ` <20240522073710.2039035-5-lingling.kong@intel.com>
2024-05-22 8:42 ` [PATCH v2 5/8] [APX NF] Support APX NF for rotate insns Kong, Lingling
[not found] ` <20240522073710.2039035-6-lingling.kong@intel.com>
2024-05-22 8:43 ` [PATCH v2 6/8] [APX NF] Support APX NF for shld/shrd Kong, Lingling
[not found] ` <20240522073710.2039035-7-lingling.kong@intel.com>
2024-05-22 8:43 ` [PATCH v2 7/8] [APX NF] Support APX NF for mul/div Kong, Lingling
[not found] ` <20240522073710.2039035-8-lingling.kong@intel.com>
2024-05-22 8:44 ` [PATCH v2 8/8] [APX NF] Support APX NF for lzcnt/tzcnt/popcnt Kong, Lingling
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=BN9PR11MB5483ED4DE65AECCB9C18433BECEB2@BN9PR11MB5483.namprd11.prod.outlook.com \
--to=lingling.kong@intel.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=hongtao.liu@intel.com \
--cc=ubizjak@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).