From: 钟居哲 <juzhe.zhong@rivai.ai>
To: rdapp.gcc <rdapp.gcc@gmail.com>,
gcc-patches <gcc-patches@gcc.gnu.org>,
palmer <palmer@dabbelt.com>, kito.cheng <kito.cheng@gmail.com>,
"Jeff Law" <jeffreyalaw@gmail.com>
Cc: rdapp.gcc <rdapp.gcc@gmail.com>
Subject: Re: Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.
Date: Thu, 16 Nov 2023 06:13:54 +0800 [thread overview]
Message-ID: <C40D904CBA588B09+202311160613537074480@rivai.ai> (raw)
In-Reply-To: <90d603a4-21c1-4500-a9e0-e7c6a7f4eb0c@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 946 bytes --]
OK. Make sense。
LGTM as long as you remove all
GET_MODE_BITSIZE (GET_MODE_INNER (<VINDEX>mode)) <= GET_MODE_BITSIZE (Pmode)
juzhe.zhong@rivai.ai
From: Robin Dapp
Date: 2023-11-16 04:30
To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.
On 11/15/23 15:29, 钟居哲 wrote:
> Could you show me the example ?
>
> It's used by handling SEW = 64 on RV32. I don't know why this patch touch this code.
Use gather_load_run-1.c with the 64-bit index patterns disabled
on rv32. We insert (mem:DI (reg:SI)) into a vector so use the
SEW = 64 demote handler. There we set vl = vl * 2 (which is correct)
but the mode (i.e. vector) just changes from DI to SI while
keeping the number of elements the same. Then we get e.g. go
from V8DI to V8SI and slide down 16 elements, losing the lower
half.
Regards
Robin
next prev parent reply other threads:[~2023-11-15 22:14 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-15 14:01 Robin Dapp
2023-11-15 14:17 ` 钟居哲
2023-11-15 14:27 ` Robin Dapp
2023-11-15 14:29 ` 钟居哲
2023-11-15 20:30 ` Robin Dapp
2023-11-15 22:13 ` 钟居哲 [this message]
2023-11-17 14:55 ` Robin Dapp
2023-11-17 15:07 ` 钟居哲
2023-11-17 15:13 ` Robin Dapp
2023-11-17 15:17 ` 钟居哲
2023-11-20 13:14 ` Robin Dapp
2023-11-20 13:20 ` juzhe.zhong
2023-11-15 14:19 ` 钟居哲
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