Register allocation (RA) doesn't affect the assembler checks since I relax the registers in assmebler checks,
all assmebler checks have their own goal. For example:

The code like this:
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + i);
+      *(vuint16mf4_t*)(out + i) = v;
+    }
+}
Assembler check:
scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\I don't care about which vector register is using since I relax register in assembler : (?:v[0-9]|v[1-2][0-9]|v3[0-1]), this means any vector register v0-v31But also I relax scalar register : (?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]), so could be any x0 - x31 of them.The only strict check is that make sure the vsetvl is hoist outside the loop meaning the location of vsetvl is outside of the Lable L[0-9]:vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]You can see the last assembler is \s+\.L[0-9] to make sure VSETVL PASS successfully do the optimization that hoist the vsetvl instruction outside the loopI try to use check-function-body but it fails since it can not recognize the Lable which is most important for such cases.


juzhe.zhong@rivai.ai
 
From: Jeff Law
Date: 2022-12-17 04:07
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Add testcases for VSETVL PASS
 
 
On 12/14/22 01:09, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> gcc/testsuite/ChangeLog:
> 
>          * gcc.target/riscv/rvv/rvv.exp: Adjust to enable tests for VSETVL PASS.
>          * gcc.target/riscv/rvv/vsetvl/dump-1.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: New test.
>          * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: New test.
So it looks like the assembler strings you're searching for are highly 
specific (across all 5 testsuite patches).  How sensitive do we expect 
these tests to be to things like register allocation giving us different 
registers and such?  I'd hate to be in a position where we're constantly 
needing to update these tests because the output is changing in 
unimportant ways.
 
Jeff