* [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR @ 2022-05-06 14:29 Qing Zhao 2022-05-06 15:58 ` Uros Bizjak 0 siblings, 1 reply; 12+ messages in thread From: Qing Zhao @ 2022-05-06 14:29 UTC (permalink / raw) To: Uros Bizjak; +Cc: gcc-patches Paul A Clarke via, kees Cook [-- Attachment #1: Type: text/plain, Size: 797 bytes --] Hi, As Kee’s requested in this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101891 ===== Currently -fzero-call-used-regs will use a pattern of: XOR regA,regA MOV regA,regB MOV regA,regC ... RET However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). Please switch to always using XOR: XOR regA,regA XOR regB,regB XOR regC,regC ... RET ======= This patch switch all MOV to XOR on i386. Bootstrapped and regresstion tested on x86_64-linux-gnu. Okay for gcc13? Thanks. Qing ========================================== [-- Attachment #2: 0001-change-mov-to-xor-fix-all-testing-cases.patch --] [-- Type: application/octet-stream, Size: 40811 bytes --] From 2f1b37364c2a03fb451d4cd01a44fac6dca77e14 Mon Sep 17 00:00:00 2001 From: Qing Zhao <qing.zhao@oracle.com> Date: Wed, 2 Feb 2022 22:54:05 +0000 Subject: [PATCH] i386: Adjust -fzero-call-used-regs to always use XOR [PR101891] Currently on i386, -fzero-call-used-regs uses a pattern of: XOR regA,regA MOV regA,regB MOV regA,regC ... RET However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). This patch will switch to always use XOR on i386: XOR regA,regA XOR regB,regB XOR regC,regC ... RET gcc/ChangeLog: * config/i386/i386.cc (zero_all_mm_registers): Use SET to zero instead of MOV for zeroing scratch registers. (ix86_zero_call_used_regs): Likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector -fno-PIC. * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector -fno-PIC. * gcc.target/i386/zero-scratch-regs-16.c: Likewise. * gcc.target/i386/zero-scratch-regs-17.c: Likewise. * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector -fno-PIC, adjust mov to xor. * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector -fno-PIC. * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector -fno-PIC, Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-23.c: Likewise. * gcc.target/i386/zero-scratch-regs-26.c: Likewise. * gcc.target/i386/zero-scratch-regs-27.c: Likewise. * gcc.target/i386/zero-scratch-regs-28.c: Likewise. * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector -fno-PIC. * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. * gcc.target/i386/zero-scratch-regs-7.c: Likewise. * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. --- gcc/config/i386/i386.cc | 76 +++++-------------- .../gcc.target/i386/zero-scratch-regs-1.c | 2 +- .../gcc.target/i386/zero-scratch-regs-10.c | 14 ++-- .../gcc.target/i386/zero-scratch-regs-13.c | 37 ++++++--- .../gcc.target/i386/zero-scratch-regs-14.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-15.c | 2 +- .../gcc.target/i386/zero-scratch-regs-16.c | 2 +- .../gcc.target/i386/zero-scratch-regs-17.c | 2 +- .../gcc.target/i386/zero-scratch-regs-18.c | 4 +- .../gcc.target/i386/zero-scratch-regs-19.c | 2 +- .../gcc.target/i386/zero-scratch-regs-2.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-20.c | 38 ++++++---- .../gcc.target/i386/zero-scratch-regs-21.c | 4 +- .../gcc.target/i386/zero-scratch-regs-22.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-23.c | 30 ++++---- .../gcc.target/i386/zero-scratch-regs-26.c | 26 +++---- .../gcc.target/i386/zero-scratch-regs-27.c | 10 +-- .../gcc.target/i386/zero-scratch-regs-28.c | 12 +-- .../gcc.target/i386/zero-scratch-regs-3.c | 2 +- .../gcc.target/i386/zero-scratch-regs-31.c | 4 +- .../gcc.target/i386/zero-scratch-regs-4.c | 2 +- .../gcc.target/i386/zero-scratch-regs-5.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-6.c | 2 +- .../gcc.target/i386/zero-scratch-regs-7.c | 2 +- .../gcc.target/i386/zero-scratch-regs-8.c | 14 ++-- .../gcc.target/i386/zero-scratch-regs-9.c | 2 +- 26 files changed, 170 insertions(+), 183 deletions(-) diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index b16df5b183e..5a24c68b7c7 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -3826,19 +3826,12 @@ zero_all_mm_registers (HARD_REG_SET need_zeroed_hardregs, if (!need_zero_all_mm) return false; - rtx zero_mmx = NULL_RTX; machine_mode mode = V4HImode; for (unsigned int regno = FIRST_MMX_REG; regno <= LAST_MMX_REG; regno++) if (regno != ret_mmx_regno) { rtx reg = gen_rtx_REG (mode, regno); - if (zero_mmx == NULL_RTX) - { - zero_mmx = reg; - emit_insn (gen_rtx_SET (reg, CONST0_RTX (mode))); - } - else - emit_move_insn (reg, zero_mmx); + emit_insn (gen_rtx_SET (reg, CONST0_RTX (mode))); } return true; } @@ -3908,11 +3901,6 @@ ix86_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) /* Now, generate instructions to zero all the other registers. */ - rtx zero_gpr = NULL_RTX; - rtx zero_vector = NULL_RTX; - rtx zero_mask = NULL_RTX; - rtx zero_mmx = NULL_RTX; - for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) { if (!TEST_HARD_REG_BIT (need_zeroed_hardregs, regno)) @@ -3930,50 +3918,24 @@ ix86_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) zero_rtx = CONST0_RTX (mode); if (mode == SImode) - if (zero_gpr == NULL_RTX) - { - zero_gpr = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - if (!TARGET_USE_MOV0 || optimize_insn_for_size_p ()) - { - rtx clob = gen_rtx_CLOBBER (VOIDmode, - gen_rtx_REG (CCmode, - FLAGS_REG)); - tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, - tmp, - clob)); - } - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_gpr); - else if (mode == V4SFmode) - if (zero_vector == NULL_RTX) - { - zero_vector = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_vector); - else if (mode == HImode) - if (zero_mask == NULL_RTX) - { - zero_mask = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_mask); - else if (mode == V4HImode) - if (zero_mmx == NULL_RTX) - { - zero_mmx = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_mmx); + { + tmp = gen_rtx_SET (reg, zero_rtx); + if (!TARGET_USE_MOV0 || optimize_insn_for_size_p ()) + { + rtx clob = gen_rtx_CLOBBER (VOIDmode, + gen_rtx_REG (CCmode, + FLAGS_REG)); + tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, + tmp, + clob)); + } + emit_insn (tmp); + } + else if (mode == V4SFmode || mode == HImode || mode == V4HImode) + { + tmp = gen_rtx_SET (reg, zero_rtx); + emit_insn (tmp); + } else gcc_unreachable (); } diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c index 1ea6de880aa..818a56f1116 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */ void foo (void) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c index 389b1142264..cbe1b5f0958 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c @@ -12,10 +12,10 @@ foo (int x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c index 07d8de7c66f..4ed036e9f88 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=all -march=corei7 -msse" } */ void foo (void) @@ -7,15 +7,28 @@ foo (void) } /* { dg-final { scan-assembler-not "vzeroall" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 15 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm0, %xmm0" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm1, %xmm1" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm2, %xmm2" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm3, %xmm3" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm4, %xmm4" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm5, %xmm5" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm6, %xmm6" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm7, %xmm7" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm8, %xmm8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm9, %xmm9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm10, %xmm10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm11, %xmm11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm12, %xmm12" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm13, %xmm13" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm14, %xmm14" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm15, %xmm15" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c index 55a272cc53f..c361c0b3afd 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c @@ -9,11 +9,11 @@ foo (void) /* { dg-final { scan-assembler-times "vzeroall" 1 } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c index d0e975cb3d3..4d45fa56b2a 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -fno-stack-protector -fno-PIC" } */ extern void foo (void) __attribute__ ((zero_call_used_regs("used"))); diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c index d41a2557d10..fb5e6ddc1cd 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all" } */ +/* { dg-options "-O2 -fzero-call-used-regs=all -fno-stack-protector -fno-PIC" } */ extern void foo (void) __attribute__ ((zero_call_used_regs("skip"))); diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c index c79fcd39d7b..10cfa12f9ca 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used -fno-stack-protector" } */ int foo (int x) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c index 6f90723cc8e..0e399d4ebb0 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used -march=corei7 -fno-stack-protector -fno-PIC" } */ float foo (float z, float y, float x) @@ -9,5 +9,5 @@ foo (float z, float y, float x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm1, %xmm2" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm2, %xmm2" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c index 491d2d56774..cb0d5ebce04 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used -march=corei7 -fno-stack-protector -fno-PIC" } */ float foo (float z, float y, float x) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c index 52406fc70aa..cb93209a8ba 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c @@ -9,11 +9,11 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c index ccd491775c2..123bd05b51e 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=all -march=corei7 -msse" } */ float foo (float z, float y, float x) @@ -8,16 +8,28 @@ foo (float z, float y, float x) } /* { dg-final { scan-assembler-not "vzeroall" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" { target { ia32 } } } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm1, %xmm\[0-9\]+" 14 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm0, %xmm0" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm1, %xmm1" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm2, %xmm2" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm3, %xmm3" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm4, %xmm4" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm5, %xmm5" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm6, %xmm6" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm7, %xmm7" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm8, %xmm8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm9, %xmm9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm10, %xmm10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm11, %xmm11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm12, %xmm12" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm13, %xmm13" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm14, %xmm14" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm15, %xmm15" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c index b3570f318c1..e8c3d9b5f3d 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -march=corei7 -fno-stack-protector -fno-PIC" } */ __attribute__ ((zero_call_used_regs("used"))) float @@ -10,5 +10,5 @@ foo (float z, float y, float x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm1, %xmm2" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm2, %xmm2" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c index b25342065e9..63adbb9d356 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c @@ -11,11 +11,11 @@ foo (void) /* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c index 69d42d732fd..a3285bed8a0 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c @@ -11,19 +11,19 @@ foo (void) /* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler "kxorw\[ \t\]+%k0, %k0, %k0" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k2" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k3" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k4" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k5" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k6" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k7" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k1, %k1, %k1" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k2, %k2, %k2" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k3, %k3, %k3" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k4, %k4, %k4" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k5, %k5, %k5" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k6, %k6, %k6" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k7, %k7, %k7" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c index 8fb5299be56..3f22375d2fa 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c @@ -8,16 +8,16 @@ foo (int x) } /* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm1" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm2" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm3" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm4" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm5" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm6" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm7" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm0, %xmm0" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm1, %xmm1" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm2, %xmm2" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm3, %xmm3" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm4, %xmm4" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm5, %xmm5" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm6, %xmm6" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm7, %xmm7" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c index 26ceacf435d..b307d107319 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c @@ -8,8 +8,8 @@ foo (int x) } /* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c index 044e4af10f0..dfa8e01dc38 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c @@ -10,9 +10,9 @@ __v2si ret_mmx (void) } /* { dg-final { scan-assembler "pxor\[ \t\]+%mm1, %mm1" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm2" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm3" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm4" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm5" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm6" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm7" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm2, %mm2" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm3, %mm3" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm4, %mm4" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm5, %mm5" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm6, %mm6" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm7, %mm7" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c index 89e69b8ba72..6cd5c4cb067 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -fno-stack-protector" } */ void foo (void) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c index afa8b337b36..5a0e53110e6 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c @@ -10,5 +10,5 @@ __v2si ret_mmx (void) } /* { dg-final { scan-assembler "pxor\[ \t\]+%mm1, %mm1" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm2" } } */ -/* { dg-final { scan-assembler-not "movq\[ \t\]+%mm1, %mm\[34567\]" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm2, %mm2" } } */ +/* { dg-final { scan-assembler-not "pxor\[ \t\]+%mm\[34567\], %mm\[34567\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c index 1e98d17df7f..becc5b8b438 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -fno-stack-protector -fno-PIC" } */ extern void foo (void) __attribute__ ((zero_call_used_regs("used-gpr"))); diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c index 56aecdafad8..4367f96a859 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c @@ -10,11 +10,11 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c index fa831857ad8..88e3156b132 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all-gpr" } */ +/* { dg-options "-O2 -fzero-call-used-regs=all-gpr -fno-stack-protector" } */ extern void foo (void) __attribute__ ((zero_call_used_regs("skip"))); diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c index 0444a21f4da..460c301ec12 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used-gpr" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used-gpr -fno-stack-protector" } */ int foo (int x) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c index 75356db63c3..0eab76933f5 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c @@ -10,10 +10,10 @@ foo (int x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c index 64755b00c39..42dcaea4988 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -fno-stack-protector" } */ extern int foo (int) __attribute__ ((zero_call_used_regs("used-gpr"))); -- 2.27.0 ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR 2022-05-06 14:29 [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR Qing Zhao @ 2022-05-06 15:58 ` Uros Bizjak 2022-05-06 16:42 ` Qing Zhao 0 siblings, 1 reply; 12+ messages in thread From: Uros Bizjak @ 2022-05-06 15:58 UTC (permalink / raw) To: Qing Zhao; +Cc: gcc-patches Paul A Clarke via, kees Cook [-- Attachment #1: Type: text/plain, Size: 3068 bytes --] On Fri, May 6, 2022 at 4:29 PM Qing Zhao <qing.zhao@oracle.com> wrote: > > Hi, > > As Kee’s requested in this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101891 > > ===== > > Currently -fzero-call-used-regs will use a pattern of: > > XOR regA,regA > MOV regA,regB > MOV regA,regC > ... > RET > > However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). > > Please switch to always using XOR: > > XOR regA,regA > XOR regB,regB > XOR regC,regC > ... > RET > > ======= > > This patch switch all MOV to XOR on i386. > > Bootstrapped and regresstion tested on x86_64-linux-gnu. > > Okay for gcc13? > > Thanks. > > Qing > > ========================================== > gcc/ChangeLog: > > * config/i386/i386.cc (zero_all_mm_registers): Use SET to zero instead > of MOV for zeroing scratch registers. > (ix86_zero_call_used_regs): Likewise. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector > -fno-PIC. > * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. > * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. > * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. > * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector > -fno-PIC. > * gcc.target/i386/zero-scratch-regs-16.c: Likewise. > * gcc.target/i386/zero-scratch-regs-17.c: Likewise. > * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector > -fno-PIC, adjust mov to xor. > * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector > -fno-PIC. > * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. > * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. > * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector > -fno-PIC, Adjust mov to xor. > * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. > * gcc.target/i386/zero-scratch-regs-23.c: Likewise. > * gcc.target/i386/zero-scratch-regs-26.c: Likewise. > * gcc.target/i386/zero-scratch-regs-27.c: Likewise. > * gcc.target/i386/zero-scratch-regs-28.c: Likewise. > * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. > * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. > * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector > -fno-PIC. > * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. > * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. > * gcc.target/i386/zero-scratch-regs-7.c: Likewise. > * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. > * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. Please use something like the attached (functionally equivalent) patch for the last hunk of your patch. Also, if possible, please use V2SImode as a generic MMX mode instead of V4HImode. OK with the above changes. Thanks, Uros. [-- Attachment #2: p.diff.txt --] [-- Type: text/plain, Size: 2154 bytes --] diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index b16df5b183e..87220278d33 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -3923,59 +3923,32 @@ ix86_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) SET_HARD_REG_BIT (zeroed_hardregs, regno); - rtx reg, tmp, zero_rtx; machine_mode mode = zero_call_used_regno_mode (regno); - reg = gen_rtx_REG (mode, regno); - zero_rtx = CONST0_RTX (mode); + rtx reg = gen_rtx_REG (mode, regno); + rtx tmp = gen_rtx_SET (reg, CONST0_RTX (mode)); - if (mode == SImode) - if (zero_gpr == NULL_RTX) - { - zero_gpr = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - if (!TARGET_USE_MOV0 || optimize_insn_for_size_p ()) - { - rtx clob = gen_rtx_CLOBBER (VOIDmode, - gen_rtx_REG (CCmode, - FLAGS_REG)); - tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, - tmp, - clob)); - } - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_gpr); - else if (mode == V4SFmode) - if (zero_vector == NULL_RTX) - { - zero_vector = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_vector); - else if (mode == HImode) - if (zero_mask == NULL_RTX) - { - zero_mask = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_mask); - else if (mode == V4HImode) - if (zero_mmx == NULL_RTX) - { - zero_mmx = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_mmx); - else - gcc_unreachable (); + switch (mode) + { + case E_SImode: + if (!TARGET_USE_MOV0 || optimize_insn_for_size_p ()) + { + rtx clob = gen_rtx_CLOBBER (VOIDmode, + gen_rtx_REG (CCmode, FLAGS_REG)); + tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob)); + } + break; + /* FALLTHRU */ + + case E_V4SFmode: + case E_HImode: + case E_V4HImode: + emit_insn (tmp); + break; + + default: + gcc_unreachable (); + } } return zeroed_hardregs; } ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR 2022-05-06 15:58 ` Uros Bizjak @ 2022-05-06 16:42 ` Qing Zhao 2022-05-07 9:06 ` Uros Bizjak 0 siblings, 1 reply; 12+ messages in thread From: Qing Zhao @ 2022-05-06 16:42 UTC (permalink / raw) To: Uros Bizjak; +Cc: gcc-patches Paul A Clarke via, kees Cook > On May 6, 2022, at 10:58 AM, Uros Bizjak <ubizjak@gmail.com> wrote: > > On Fri, May 6, 2022 at 4:29 PM Qing Zhao <qing.zhao@oracle.com> wrote: >> >> Hi, >> >> As Kee’s requested in this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101891 >> >> ===== >> >> Currently -fzero-call-used-regs will use a pattern of: >> >> XOR regA,regA >> MOV regA,regB >> MOV regA,regC >> ... >> RET >> >> However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). >> >> Please switch to always using XOR: >> >> XOR regA,regA >> XOR regB,regB >> XOR regC,regC >> ... >> RET >> >> ======= >> >> This patch switch all MOV to XOR on i386. >> >> Bootstrapped and regresstion tested on x86_64-linux-gnu. >> >> Okay for gcc13? >> >> Thanks. >> >> Qing >> >> ========================================== > >> gcc/ChangeLog: >> >> * config/i386/i386.cc (zero_all_mm_registers): Use SET to zero instead >> of MOV for zeroing scratch registers. >> (ix86_zero_call_used_regs): Likewise. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector >> -fno-PIC. >> * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. >> * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. >> * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. >> * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector >> -fno-PIC. >> * gcc.target/i386/zero-scratch-regs-16.c: Likewise. >> * gcc.target/i386/zero-scratch-regs-17.c: Likewise. >> * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector >> -fno-PIC, adjust mov to xor. >> * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector >> -fno-PIC. >> * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. >> * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. >> * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector >> -fno-PIC, Adjust mov to xor. >> * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. >> * gcc.target/i386/zero-scratch-regs-23.c: Likewise. >> * gcc.target/i386/zero-scratch-regs-26.c: Likewise. >> * gcc.target/i386/zero-scratch-regs-27.c: Likewise. >> * gcc.target/i386/zero-scratch-regs-28.c: Likewise. >> * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. >> * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. >> * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector >> -fno-PIC. >> * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. >> * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. >> * gcc.target/i386/zero-scratch-regs-7.c: Likewise. >> * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. >> * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. > > Please use something like the attached (functionally equivalent) patch > for the last hunk of your patch. Sure, I will update the code. > > Also, if possible, please use V2SImode as a generic MMX mode instead > of V4HImode. What’s the major purpose of this change? thanks. Qing > > OK with the above changes. > > Thanks, > Uros. > <p.diff.txt> ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR 2022-05-06 16:42 ` Qing Zhao @ 2022-05-07 9:06 ` Uros Bizjak 2022-05-09 15:42 ` Qing Zhao 2022-05-09 15:44 ` Qing Zhao 0 siblings, 2 replies; 12+ messages in thread From: Uros Bizjak @ 2022-05-07 9:06 UTC (permalink / raw) To: Qing Zhao; +Cc: gcc-patches Paul A Clarke via, kees Cook On Fri, May 6, 2022 at 6:42 PM Qing Zhao <qing.zhao@oracle.com> wrote: > > > > > On May 6, 2022, at 10:58 AM, Uros Bizjak <ubizjak@gmail.com> wrote: > > > > On Fri, May 6, 2022 at 4:29 PM Qing Zhao <qing.zhao@oracle.com> wrote: > >> > >> Hi, > >> > >> As Kee’s requested in this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101891 > >> > >> ===== > >> > >> Currently -fzero-call-used-regs will use a pattern of: > >> > >> XOR regA,regA > >> MOV regA,regB > >> MOV regA,regC > >> ... > >> RET > >> > >> However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). > >> > >> Please switch to always using XOR: > >> > >> XOR regA,regA > >> XOR regB,regB > >> XOR regC,regC > >> ... > >> RET > >> > >> ======= > >> > >> This patch switch all MOV to XOR on i386. > >> > >> Bootstrapped and regresstion tested on x86_64-linux-gnu. > >> > >> Okay for gcc13? > >> > >> Thanks. > >> > >> Qing > >> > >> ========================================== > > > >> gcc/ChangeLog: > >> > >> * config/i386/i386.cc (zero_all_mm_registers): Use SET to zero instead > >> of MOV for zeroing scratch registers. > >> (ix86_zero_call_used_regs): Likewise. > >> > >> gcc/testsuite/ChangeLog: > >> > >> * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector > >> -fno-PIC. > >> * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. > >> * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. > >> * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. > >> * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector > >> -fno-PIC. > >> * gcc.target/i386/zero-scratch-regs-16.c: Likewise. > >> * gcc.target/i386/zero-scratch-regs-17.c: Likewise. > >> * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector > >> -fno-PIC, adjust mov to xor. > >> * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector > >> -fno-PIC. > >> * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. > >> * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. > >> * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector > >> -fno-PIC, Adjust mov to xor. > >> * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. > >> * gcc.target/i386/zero-scratch-regs-23.c: Likewise. > >> * gcc.target/i386/zero-scratch-regs-26.c: Likewise. > >> * gcc.target/i386/zero-scratch-regs-27.c: Likewise. > >> * gcc.target/i386/zero-scratch-regs-28.c: Likewise. > >> * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. > >> * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. > >> * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector > >> -fno-PIC. > >> * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. > >> * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. > >> * gcc.target/i386/zero-scratch-regs-7.c: Likewise. > >> * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. > >> * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. > > > > Please use something like the attached (functionally equivalent) patch > > for the last hunk of your patch. > > Sure, I will update the code. > > > > Also, if possible, please use V2SImode as a generic MMX mode instead > > of V4HImode. > What’s the major purpose of this change? Although the generated code is the same, V2SI is used as a "generic" MMX move insn in the same way V2DI is used to describe generic SSE move instruction. Uros. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR 2022-05-07 9:06 ` Uros Bizjak @ 2022-05-09 15:42 ` Qing Zhao 2022-05-09 15:44 ` Qing Zhao 1 sibling, 0 replies; 12+ messages in thread From: Qing Zhao @ 2022-05-09 15:42 UTC (permalink / raw) To: Uros Bizjak; +Cc: gcc-patches Paul A Clarke via, kees Cook > On May 7, 2022, at 4:06 AM, Uros Bizjak <ubizjak@gmail.com> wrote: > > On Fri, May 6, 2022 at 6:42 PM Qing Zhao <qing.zhao@oracle.com> wrote: >> >> >> >>> On May 6, 2022, at 10:58 AM, Uros Bizjak <ubizjak@gmail.com> wrote: >>> >>> On Fri, May 6, 2022 at 4:29 PM Qing Zhao <qing.zhao@oracle.com> wrote: >>>> >>>> Hi, >>>> >>>> As Kee’s requested in this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101891 >>>> >>>> ===== >>>> >>>> Currently -fzero-call-used-regs will use a pattern of: >>>> >>>> XOR regA,regA >>>> MOV regA,regB >>>> MOV regA,regC >>>> ... >>>> RET >>>> >>>> However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). >>>> >>>> Please switch to always using XOR: >>>> >>>> XOR regA,regA >>>> XOR regB,regB >>>> XOR regC,regC >>>> ... >>>> RET >>>> >>>> ======= >>>> >>>> This patch switch all MOV to XOR on i386. >>>> >>>> Bootstrapped and regresstion tested on x86_64-linux-gnu. >>>> >>>> Okay for gcc13? >>>> >>>> Thanks. >>>> >>>> Qing >>>> >>>> ========================================== >>> >>>> gcc/ChangeLog: >>>> >>>> * config/i386/i386.cc (zero_all_mm_registers): Use SET to zero instead >>>> of MOV for zeroing scratch registers. >>>> (ix86_zero_call_used_regs): Likewise. >>>> >>>> gcc/testsuite/ChangeLog: >>>> >>>> * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector >>>> -fno-PIC. >>>> * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. >>>> * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector >>>> -fno-PIC. >>>> * gcc.target/i386/zero-scratch-regs-16.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-17.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector >>>> -fno-PIC, adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector >>>> -fno-PIC. >>>> * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. >>>> * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector >>>> -fno-PIC, Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-23.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-26.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-27.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-28.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. >>>> * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector >>>> -fno-PIC. >>>> * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. >>>> * gcc.target/i386/zero-scratch-regs-7.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. >>> >>> Please use something like the attached (functionally equivalent) patch >>> for the last hunk of your patch. >> >> Sure, I will update the code. >>> >>> Also, if possible, please use V2SImode as a generic MMX mode instead >>> of V4HImode. >> What’s the major purpose of this change? > > Although the generated code is the same, V2SI is used as a "generic" > MMX move insn in the same way V2DI is used to describe generic SSE > move instruction. Thank you!. FYI, I just committed the patch to the trunk (with updating as you suggested): https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=0b86943aca51175968e40bbb6f2662dfe3fbfe59 Qing > > Uros. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR 2022-05-07 9:06 ` Uros Bizjak 2022-05-09 15:42 ` Qing Zhao @ 2022-05-09 15:44 ` Qing Zhao 2022-05-09 18:25 ` Uros Bizjak 1 sibling, 1 reply; 12+ messages in thread From: Qing Zhao @ 2022-05-09 15:44 UTC (permalink / raw) To: Uros Bizjak; +Cc: gcc-patches Paul A Clarke via, kees Cook Another question: I think that this patch might need to be back ported to Gcc12 and GCC11. What’s your opinion on this? If so, when can I backport it? thanks. Qing > On May 7, 2022, at 4:06 AM, Uros Bizjak <ubizjak@gmail.com> wrote: > > On Fri, May 6, 2022 at 6:42 PM Qing Zhao <qing.zhao@oracle.com> wrote: >> >> >> >>> On May 6, 2022, at 10:58 AM, Uros Bizjak <ubizjak@gmail.com> wrote: >>> >>> On Fri, May 6, 2022 at 4:29 PM Qing Zhao <qing.zhao@oracle.com> wrote: >>>> >>>> Hi, >>>> >>>> As Kee’s requested in this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101891 >>>> >>>> ===== >>>> >>>> Currently -fzero-call-used-regs will use a pattern of: >>>> >>>> XOR regA,regA >>>> MOV regA,regB >>>> MOV regA,regC >>>> ... >>>> RET >>>> >>>> However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). >>>> >>>> Please switch to always using XOR: >>>> >>>> XOR regA,regA >>>> XOR regB,regB >>>> XOR regC,regC >>>> ... >>>> RET >>>> >>>> ======= >>>> >>>> This patch switch all MOV to XOR on i386. >>>> >>>> Bootstrapped and regresstion tested on x86_64-linux-gnu. >>>> >>>> Okay for gcc13? >>>> >>>> Thanks. >>>> >>>> Qing >>>> >>>> ========================================== >>> >>>> gcc/ChangeLog: >>>> >>>> * config/i386/i386.cc (zero_all_mm_registers): Use SET to zero instead >>>> of MOV for zeroing scratch registers. >>>> (ix86_zero_call_used_regs): Likewise. >>>> >>>> gcc/testsuite/ChangeLog: >>>> >>>> * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector >>>> -fno-PIC. >>>> * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. >>>> * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector >>>> -fno-PIC. >>>> * gcc.target/i386/zero-scratch-regs-16.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-17.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector >>>> -fno-PIC, adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector >>>> -fno-PIC. >>>> * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. >>>> * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector >>>> -fno-PIC, Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-23.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-26.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-27.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-28.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. >>>> * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector >>>> -fno-PIC. >>>> * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. >>>> * gcc.target/i386/zero-scratch-regs-7.c: Likewise. >>>> * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. >>>> * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. >>> >>> Please use something like the attached (functionally equivalent) patch >>> for the last hunk of your patch. >> >> Sure, I will update the code. >>> >>> Also, if possible, please use V2SImode as a generic MMX mode instead >>> of V4HImode. >> What’s the major purpose of this change? > > Although the generated code is the same, V2SI is used as a "generic" > MMX move insn in the same way V2DI is used to describe generic SSE > move instruction. > > Uros. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR 2022-05-09 15:44 ` Qing Zhao @ 2022-05-09 18:25 ` Uros Bizjak 2022-05-10 6:12 ` Richard Biener 0 siblings, 1 reply; 12+ messages in thread From: Uros Bizjak @ 2022-05-09 18:25 UTC (permalink / raw) To: Qing Zhao Cc: gcc-patches Paul A Clarke via, kees Cook, Jakub Jelinek, Richard Biener On Mon, May 9, 2022 at 5:44 PM Qing Zhao <qing.zhao@oracle.com> wrote: > > Another question: > > I think that this patch might need to be back ported to Gcc12 and GCC11. > > What’s your opinion on this? It is not a regression, so following general rules, the patch should not be backported. OTOH, the patch creates functionally equivalent code, better in some security aspects. The functionality is also hidden behind some non-default flag, so I think if release managers (CC'd) are OK with the backport, I'd give it a technical approval. > If so, when can I backport it? Let's keep it in the mainline for a week or two, before backporting it to non-EoL branches. Uros. > > thanks. > > Qing > > > On May 7, 2022, at 4:06 AM, Uros Bizjak <ubizjak@gmail.com> wrote: > > > > On Fri, May 6, 2022 at 6:42 PM Qing Zhao <qing.zhao@oracle.com> wrote: > >> > >> > >> > >>> On May 6, 2022, at 10:58 AM, Uros Bizjak <ubizjak@gmail.com> wrote: > >>> > >>> On Fri, May 6, 2022 at 4:29 PM Qing Zhao <qing.zhao@oracle.com> wrote: > >>>> > >>>> Hi, > >>>> > >>>> As Kee’s requested in this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101891 > >>>> > >>>> ===== > >>>> > >>>> Currently -fzero-call-used-regs will use a pattern of: > >>>> > >>>> XOR regA,regA > >>>> MOV regA,regB > >>>> MOV regA,regC > >>>> ... > >>>> RET > >>>> > >>>> However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). > >>>> > >>>> Please switch to always using XOR: > >>>> > >>>> XOR regA,regA > >>>> XOR regB,regB > >>>> XOR regC,regC > >>>> ... > >>>> RET > >>>> > >>>> ======= > >>>> > >>>> This patch switch all MOV to XOR on i386. > >>>> > >>>> Bootstrapped and regresstion tested on x86_64-linux-gnu. > >>>> > >>>> Okay for gcc13? > >>>> > >>>> Thanks. > >>>> > >>>> Qing > >>>> > >>>> ========================================== > >>> > >>>> gcc/ChangeLog: > >>>> > >>>> * config/i386/i386.cc (zero_all_mm_registers): Use SET to zero instead > >>>> of MOV for zeroing scratch registers. > >>>> (ix86_zero_call_used_regs): Likewise. > >>>> > >>>> gcc/testsuite/ChangeLog: > >>>> > >>>> * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector > >>>> -fno-PIC. > >>>> * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. > >>>> * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. > >>>> * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. > >>>> * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector > >>>> -fno-PIC. > >>>> * gcc.target/i386/zero-scratch-regs-16.c: Likewise. > >>>> * gcc.target/i386/zero-scratch-regs-17.c: Likewise. > >>>> * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector > >>>> -fno-PIC, adjust mov to xor. > >>>> * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector > >>>> -fno-PIC. > >>>> * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. > >>>> * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. > >>>> * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector > >>>> -fno-PIC, Adjust mov to xor. > >>>> * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. > >>>> * gcc.target/i386/zero-scratch-regs-23.c: Likewise. > >>>> * gcc.target/i386/zero-scratch-regs-26.c: Likewise. > >>>> * gcc.target/i386/zero-scratch-regs-27.c: Likewise. > >>>> * gcc.target/i386/zero-scratch-regs-28.c: Likewise. > >>>> * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. > >>>> * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. > >>>> * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector > >>>> -fno-PIC. > >>>> * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. > >>>> * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. > >>>> * gcc.target/i386/zero-scratch-regs-7.c: Likewise. > >>>> * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. > >>>> * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. > >>> > >>> Please use something like the attached (functionally equivalent) patch > >>> for the last hunk of your patch. > >> > >> Sure, I will update the code. > >>> > >>> Also, if possible, please use V2SImode as a generic MMX mode instead > >>> of V4HImode. > >> What’s the major purpose of this change? > > > > Although the generated code is the same, V2SI is used as a "generic" > > MMX move insn in the same way V2DI is used to describe generic SSE > > move instruction. > > > > Uros. > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR 2022-05-09 18:25 ` Uros Bizjak @ 2022-05-10 6:12 ` Richard Biener 2022-05-10 13:38 ` Qing Zhao 0 siblings, 1 reply; 12+ messages in thread From: Richard Biener @ 2022-05-10 6:12 UTC (permalink / raw) To: Uros Bizjak Cc: Qing Zhao, gcc-patches Paul A Clarke via, kees Cook, Jakub Jelinek On Mon, 9 May 2022, Uros Bizjak wrote: > On Mon, May 9, 2022 at 5:44 PM Qing Zhao <qing.zhao@oracle.com> wrote: > > > > Another question: > > > > I think that this patch might need to be back ported to Gcc12 and GCC11. > > > > What?s your opinion on this? > > It is not a regression, so following general rules, the patch should > not be backported. OTOH, the patch creates functionally equivalent > code, better in some security aspects. The functionality is also > hidden behind some non-default flag, so I think if release managers > (CC'd) are OK with the backport, I'd give it a technical approval. > > > If so, when can I backport it? > > Let's keep it in the mainline for a week or two, before backporting it > to non-EoL branches. OK from my POV after a week or two on trunk. Richard. > Uros. > > > > > thanks. > > > > Qing > > > > > On May 7, 2022, at 4:06 AM, Uros Bizjak <ubizjak@gmail.com> wrote: > > > > > > On Fri, May 6, 2022 at 6:42 PM Qing Zhao <qing.zhao@oracle.com> wrote: > > >> > > >> > > >> > > >>> On May 6, 2022, at 10:58 AM, Uros Bizjak <ubizjak@gmail.com> wrote: > > >>> > > >>> On Fri, May 6, 2022 at 4:29 PM Qing Zhao <qing.zhao@oracle.com> wrote: > > >>>> > > >>>> Hi, > > >>>> > > >>>> As Kee?s requested in this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101891 > > >>>> > > >>>> ===== > > >>>> > > >>>> Currently -fzero-call-used-regs will use a pattern of: > > >>>> > > >>>> XOR regA,regA > > >>>> MOV regA,regB > > >>>> MOV regA,regC > > >>>> ... > > >>>> RET > > >>>> > > >>>> However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). > > >>>> > > >>>> Please switch to always using XOR: > > >>>> > > >>>> XOR regA,regA > > >>>> XOR regB,regB > > >>>> XOR regC,regC > > >>>> ... > > >>>> RET > > >>>> > > >>>> ======= > > >>>> > > >>>> This patch switch all MOV to XOR on i386. > > >>>> > > >>>> Bootstrapped and regresstion tested on x86_64-linux-gnu. > > >>>> > > >>>> Okay for gcc13? > > >>>> > > >>>> Thanks. > > >>>> > > >>>> Qing > > >>>> > > >>>> ========================================== > > >>> > > >>>> gcc/ChangeLog: > > >>>> > > >>>> * config/i386/i386.cc (zero_all_mm_registers): Use SET to zero instead > > >>>> of MOV for zeroing scratch registers. > > >>>> (ix86_zero_call_used_regs): Likewise. > > >>>> > > >>>> gcc/testsuite/ChangeLog: > > >>>> > > >>>> * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector > > >>>> -fno-PIC. > > >>>> * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. > > >>>> * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. > > >>>> * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. > > >>>> * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector > > >>>> -fno-PIC. > > >>>> * gcc.target/i386/zero-scratch-regs-16.c: Likewise. > > >>>> * gcc.target/i386/zero-scratch-regs-17.c: Likewise. > > >>>> * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector > > >>>> -fno-PIC, adjust mov to xor. > > >>>> * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector > > >>>> -fno-PIC. > > >>>> * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. > > >>>> * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. > > >>>> * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector > > >>>> -fno-PIC, Adjust mov to xor. > > >>>> * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. > > >>>> * gcc.target/i386/zero-scratch-regs-23.c: Likewise. > > >>>> * gcc.target/i386/zero-scratch-regs-26.c: Likewise. > > >>>> * gcc.target/i386/zero-scratch-regs-27.c: Likewise. > > >>>> * gcc.target/i386/zero-scratch-regs-28.c: Likewise. > > >>>> * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. > > >>>> * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. > > >>>> * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector > > >>>> -fno-PIC. > > >>>> * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. > > >>>> * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. > > >>>> * gcc.target/i386/zero-scratch-regs-7.c: Likewise. > > >>>> * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. > > >>>> * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. > > >>> > > >>> Please use something like the attached (functionally equivalent) patch > > >>> for the last hunk of your patch. > > >> > > >> Sure, I will update the code. > > >>> > > >>> Also, if possible, please use V2SImode as a generic MMX mode instead > > >>> of V4HImode. > > >> What?s the major purpose of this change? > > > > > > Although the generated code is the same, V2SI is used as a "generic" > > > MMX move insn in the same way V2DI is used to describe generic SSE > > > move instruction. > > > > > > Uros. > > > -- Richard Biener <rguenther@suse.de> SUSE Software Solutions Germany GmbH, Maxfeldstrasse 5, 90409 Nuernberg, Germany; GF: Felix Imend ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR 2022-05-10 6:12 ` Richard Biener @ 2022-05-10 13:38 ` Qing Zhao 2022-05-23 15:16 ` Back porting to GCC11/GCC12: " Qing Zhao 0 siblings, 1 reply; 12+ messages in thread From: Qing Zhao @ 2022-05-10 13:38 UTC (permalink / raw) To: Richard Biener Cc: Uros Bizjak, gcc-patches Paul A Clarke via, kees Cook, Jakub Jelinek > On May 10, 2022, at 1:12 AM, Richard Biener <rguenther@suse.de> wrote: > > On Mon, 9 May 2022, Uros Bizjak wrote: > >> On Mon, May 9, 2022 at 5:44 PM Qing Zhao <qing.zhao@oracle.com> wrote: >>> >>> Another question: >>> >>> I think that this patch might need to be back ported to Gcc12 and GCC11. >>> >>> What?s your opinion on this? >> >> It is not a regression, so following general rules, the patch should >> not be backported. OTOH, the patch creates functionally equivalent >> code, better in some security aspects. The functionality is also >> hidden behind some non-default flag, so I think if release managers >> (CC'd) are OK with the backport, I'd give it a technical approval. >> >>> If so, when can I backport it? >> >> Let's keep it in the mainline for a week or two, before backporting it >> to non-EoL branches. > > OK from my POV after a week or two on trunk. Sure, I will do the back porting after two weeks. thanks. Qing > > Richard. > >> Uros. >> >>> >>> thanks. >>> >>> Qing >>> >>>> On May 7, 2022, at 4:06 AM, Uros Bizjak <ubizjak@gmail.com> wrote: >>>> >>>> On Fri, May 6, 2022 at 6:42 PM Qing Zhao <qing.zhao@oracle.com> wrote: >>>>> >>>>> >>>>> >>>>>> On May 6, 2022, at 10:58 AM, Uros Bizjak <ubizjak@gmail.com> wrote: >>>>>> >>>>>> On Fri, May 6, 2022 at 4:29 PM Qing Zhao <qing.zhao@oracle.com> wrote: >>>>>>> >>>>>>> Hi, >>>>>>> >>>>>>> As Kee?s requested in this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101891 >>>>>>> >>>>>>> ===== >>>>>>> >>>>>>> Currently -fzero-call-used-regs will use a pattern of: >>>>>>> >>>>>>> XOR regA,regA >>>>>>> MOV regA,regB >>>>>>> MOV regA,regC >>>>>>> ... >>>>>>> RET >>>>>>> >>>>>>> However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). >>>>>>> >>>>>>> Please switch to always using XOR: >>>>>>> >>>>>>> XOR regA,regA >>>>>>> XOR regB,regB >>>>>>> XOR regC,regC >>>>>>> ... >>>>>>> RET >>>>>>> >>>>>>> ======= >>>>>>> >>>>>>> This patch switch all MOV to XOR on i386. >>>>>>> >>>>>>> Bootstrapped and regresstion tested on x86_64-linux-gnu. >>>>>>> >>>>>>> Okay for gcc13? >>>>>>> >>>>>>> Thanks. >>>>>>> >>>>>>> Qing >>>>>>> >>>>>>> ========================================== >>>>>> >>>>>>> gcc/ChangeLog: >>>>>>> >>>>>>> * config/i386/i386.cc (zero_all_mm_registers): Use SET to zero instead >>>>>>> of MOV for zeroing scratch registers. >>>>>>> (ix86_zero_call_used_regs): Likewise. >>>>>>> >>>>>>> gcc/testsuite/ChangeLog: >>>>>>> >>>>>>> * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector >>>>>>> -fno-PIC. >>>>>>> * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. >>>>>>> * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. >>>>>>> * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. >>>>>>> * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector >>>>>>> -fno-PIC. >>>>>>> * gcc.target/i386/zero-scratch-regs-16.c: Likewise. >>>>>>> * gcc.target/i386/zero-scratch-regs-17.c: Likewise. >>>>>>> * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector >>>>>>> -fno-PIC, adjust mov to xor. >>>>>>> * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector >>>>>>> -fno-PIC. >>>>>>> * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. >>>>>>> * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. >>>>>>> * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector >>>>>>> -fno-PIC, Adjust mov to xor. >>>>>>> * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. >>>>>>> * gcc.target/i386/zero-scratch-regs-23.c: Likewise. >>>>>>> * gcc.target/i386/zero-scratch-regs-26.c: Likewise. >>>>>>> * gcc.target/i386/zero-scratch-regs-27.c: Likewise. >>>>>>> * gcc.target/i386/zero-scratch-regs-28.c: Likewise. >>>>>>> * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. >>>>>>> * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. >>>>>>> * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector >>>>>>> -fno-PIC. >>>>>>> * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. >>>>>>> * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. >>>>>>> * gcc.target/i386/zero-scratch-regs-7.c: Likewise. >>>>>>> * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. >>>>>>> * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. >>>>>> >>>>>> Please use something like the attached (functionally equivalent) patch >>>>>> for the last hunk of your patch. >>>>> >>>>> Sure, I will update the code. >>>>>> >>>>>> Also, if possible, please use V2SImode as a generic MMX mode instead >>>>>> of V4HImode. >>>>> What?s the major purpose of this change? >>>> >>>> Although the generated code is the same, V2SI is used as a "generic" >>>> MMX move insn in the same way V2DI is used to describe generic SSE >>>> move instruction. >>>> >>>> Uros. >>> >> > > -- > Richard Biener <rguenther@suse.de> > SUSE Software Solutions Germany GmbH, Maxfeldstrasse 5, 90409 Nuernberg, > Germany; GF: Felix Imend ^ permalink raw reply [flat|nested] 12+ messages in thread
* Back porting to GCC11/GCC12: Re: [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR 2022-05-10 13:38 ` Qing Zhao @ 2022-05-23 15:16 ` Qing Zhao 2022-05-24 6:19 ` Richard Biener 0 siblings, 1 reply; 12+ messages in thread From: Qing Zhao @ 2022-05-23 15:16 UTC (permalink / raw) To: Richard Biener, Jakub Jelinek; +Cc: gcc-patches Paul A Clarke via, kees Cook [-- Attachment #1: Type: text/plain, Size: 5760 bytes --] Hi, I have added the patch to GCC11 and GCC12 in my local area and bootstrapped and regress tested on both x86 and aarch64, no any issues. Can I committed them to both GCC11 and GCC12 branches? Thanks. > On May 10, 2022, at 8:38 AM, Qing Zhao via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > > >> On May 10, 2022, at 1:12 AM, Richard Biener <rguenther@suse.de> wrote: >> >> On Mon, 9 May 2022, Uros Bizjak wrote: >> >>> On Mon, May 9, 2022 at 5:44 PM Qing Zhao <qing.zhao@oracle.com> wrote: >>>> >>>> Another question: >>>> >>>> I think that this patch might need to be back ported to Gcc12 and GCC11. >>>> >>>> What?s your opinion on this? >>> >>> It is not a regression, so following general rules, the patch should >>> not be backported. OTOH, the patch creates functionally equivalent >>> code, better in some security aspects. The functionality is also >>> hidden behind some non-default flag, so I think if release managers >>> (CC'd) are OK with the backport, I'd give it a technical approval. >>> >>>> If so, when can I backport it? >>> >>> Let's keep it in the mainline for a week or two, before backporting it >>> to non-EoL branches. >> >> OK from my POV after a week or two on trunk. > > Sure, I will do the back porting after two weeks. > > thanks. > > Qing >> >> Richard. >> >>> Uros. >>> >>>> >>>> thanks. >>>> >>>> Qing >>>> >>>>> On May 7, 2022, at 4:06 AM, Uros Bizjak <ubizjak@gmail.com> wrote: >>>>> >>>>> On Fri, May 6, 2022 at 6:42 PM Qing Zhao <qing.zhao@oracle.com> wrote: >>>>>> >>>>>> >>>>>> >>>>>>> On May 6, 2022, at 10:58 AM, Uros Bizjak <ubizjak@gmail.com> wrote: >>>>>>> >>>>>>> On Fri, May 6, 2022 at 4:29 PM Qing Zhao <qing.zhao@oracle.com> wrote: >>>>>>>> >>>>>>>> Hi, >>>>>>>> >>>>>>>> As Kee?s requested in this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101891 >>>>>>>> >>>>>>>> ===== >>>>>>>> >>>>>>>> Currently -fzero-call-used-regs will use a pattern of: >>>>>>>> >>>>>>>> XOR regA,regA >>>>>>>> MOV regA,regB >>>>>>>> MOV regA,regC >>>>>>>> ... >>>>>>>> RET >>>>>>>> >>>>>>>> However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). >>>>>>>> >>>>>>>> Please switch to always using XOR: >>>>>>>> >>>>>>>> XOR regA,regA >>>>>>>> XOR regB,regB >>>>>>>> XOR regC,regC >>>>>>>> ... >>>>>>>> RET >>>>>>>> >>>>>>>> ======= >>>>>>>> >>>>>>>> This patch switch all MOV to XOR on i386. >>>>>>>> >>>>>>>> Bootstrapped and regresstion tested on x86_64-linux-gnu. >>>>>>>> >>>>>>>> Okay for gcc13? >>>>>>>> >>>>>>>> Thanks. >>>>>>>> >>>>>>>> Qing >>>>>>>> >>>>>>>> ========================================== >>>>>>> >>>>>>>> gcc/ChangeLog: >>>>>>>> >>>>>>>> * config/i386/i386.cc (zero_all_mm_registers): Use SET to zero instead >>>>>>>> of MOV for zeroing scratch registers. >>>>>>>> (ix86_zero_call_used_regs): Likewise. >>>>>>>> >>>>>>>> gcc/testsuite/ChangeLog: >>>>>>>> >>>>>>>> * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector >>>>>>>> -fno-PIC. >>>>>>>> * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. >>>>>>>> * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. >>>>>>>> * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. >>>>>>>> * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector >>>>>>>> -fno-PIC. >>>>>>>> * gcc.target/i386/zero-scratch-regs-16.c: Likewise. >>>>>>>> * gcc.target/i386/zero-scratch-regs-17.c: Likewise. >>>>>>>> * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector >>>>>>>> -fno-PIC, adjust mov to xor. >>>>>>>> * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector >>>>>>>> -fno-PIC. >>>>>>>> * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. >>>>>>>> * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. >>>>>>>> * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector >>>>>>>> -fno-PIC, Adjust mov to xor. >>>>>>>> * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. >>>>>>>> * gcc.target/i386/zero-scratch-regs-23.c: Likewise. >>>>>>>> * gcc.target/i386/zero-scratch-regs-26.c: Likewise. >>>>>>>> * gcc.target/i386/zero-scratch-regs-27.c: Likewise. >>>>>>>> * gcc.target/i386/zero-scratch-regs-28.c: Likewise. >>>>>>>> * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. >>>>>>>> * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. >>>>>>>> * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector >>>>>>>> -fno-PIC. >>>>>>>> * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. >>>>>>>> * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. >>>>>>>> * gcc.target/i386/zero-scratch-regs-7.c: Likewise. >>>>>>>> * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. >>>>>>>> * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. >>>>>>> >>>>>>> Please use something like the attached (functionally equivalent) patch >>>>>>> for the last hunk of your patch. >>>>>> >>>>>> Sure, I will update the code. >>>>>>> >>>>>>> Also, if possible, please use V2SImode as a generic MMX mode instead >>>>>>> of V4HImode. >>>>>> What?s the major purpose of this change? >>>>> >>>>> Although the generated code is the same, V2SI is used as a "generic" >>>>> MMX move insn in the same way V2DI is used to describe generic SSE >>>>> move instruction. >>>>> >>>>> Uros. >>>> >>> >> >> -- >> Richard Biener <rguenther@suse.de> >> SUSE Software Solutions Germany GmbH, Maxfeldstrasse 5, 90409 Nuernberg, >> Germany; GF: Felix Imend [-- Attachment #2: 0001-i386-Adjust-fzero-call-used-regs-to-always-use-XOR-P.patch.gcc11 --] [-- Type: application/octet-stream, Size: 41607 bytes --] From 8c3c41860467c3b0e7edc619c3458190d9ce9e18 Mon Sep 17 00:00:00 2001 From: Qing Zhao <qing.zhao@oracle.com> Date: Fri, 20 May 2022 20:22:10 +0000 Subject: [PATCH] i386: Adjust -fzero-call-used-regs to always use XOR [PR101891] Currently on i386, -fzero-call-used-regs uses a pattern of: XOR regA,regA MOV regA,regB MOV regA,regC ... RET However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). This patch will switch to always use XOR on i386: XOR regA,regA XOR regB,regB XOR regC,regC ... RET gcc/ChangeLog: PR target/101891 * config/i386/i386.c (zero_call_used_regno_mode): use V2SImode as a generic MMX mode instead of V4HImode. (zero_all_mm_registers): Use SET to zero instead of MOV for zeroing scratch registers. (ix86_zero_call_used_regs): Likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector -fno-PIC. * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector -fno-PIC. * gcc.target/i386/zero-scratch-regs-16.c: Likewise. * gcc.target/i386/zero-scratch-regs-17.c: Likewise. * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector -fno-PIC, adjust mov to xor. * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector -fno-PIC. * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector -fno-PIC, Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-23.c: Likewise. * gcc.target/i386/zero-scratch-regs-26.c: Likewise. * gcc.target/i386/zero-scratch-regs-27.c: Likewise. * gcc.target/i386/zero-scratch-regs-28.c: Likewise. * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector -fno-PIC. * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. * gcc.target/i386/zero-scratch-regs-7.c: Likewise. * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. (cherry picked from commit 0b86943aca51175968e40bbb6f2662dfe3fbfe59) --- gcc/config/i386/i386.c | 93 ++++++------------- .../gcc.target/i386/zero-scratch-regs-1.c | 2 +- .../gcc.target/i386/zero-scratch-regs-10.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-13.c | 37 +++++--- .../gcc.target/i386/zero-scratch-regs-14.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-15.c | 2 +- .../gcc.target/i386/zero-scratch-regs-16.c | 2 +- .../gcc.target/i386/zero-scratch-regs-17.c | 2 +- .../gcc.target/i386/zero-scratch-regs-18.c | 4 +- .../gcc.target/i386/zero-scratch-regs-19.c | 2 +- .../gcc.target/i386/zero-scratch-regs-2.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-20.c | 38 +++++--- .../gcc.target/i386/zero-scratch-regs-21.c | 4 +- .../gcc.target/i386/zero-scratch-regs-22.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-23.c | 30 +++--- .../gcc.target/i386/zero-scratch-regs-26.c | 26 +++--- .../gcc.target/i386/zero-scratch-regs-27.c | 10 +- .../gcc.target/i386/zero-scratch-regs-28.c | 12 +-- .../gcc.target/i386/zero-scratch-regs-3.c | 2 +- .../gcc.target/i386/zero-scratch-regs-31.c | 4 +- .../gcc.target/i386/zero-scratch-regs-4.c | 2 +- .../gcc.target/i386/zero-scratch-regs-5.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-6.c | 2 +- .../gcc.target/i386/zero-scratch-regs-7.c | 2 +- .../gcc.target/i386/zero-scratch-regs-8.c | 14 +-- .../gcc.target/i386/zero-scratch-regs-9.c | 2 +- 26 files changed, 180 insertions(+), 192 deletions(-) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 16fde42a9e0..a90f64e9d39 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -3607,7 +3607,7 @@ zero_call_used_regno_mode (const unsigned int regno) else if (MASK_REGNO_P (regno)) return HImode; else if (MMX_REGNO_P (regno)) - return V4HImode; + return V2SImode; else gcc_unreachable (); } @@ -3726,19 +3726,12 @@ zero_all_mm_registers (HARD_REG_SET need_zeroed_hardregs, if (!need_zero_all_mm) return false; - rtx zero_mmx = NULL_RTX; - machine_mode mode = V4HImode; + machine_mode mode = V2SImode; for (unsigned int regno = FIRST_MMX_REG; regno <= LAST_MMX_REG; regno++) if (regno != ret_mmx_regno) { rtx reg = gen_rtx_REG (mode, regno); - if (zero_mmx == NULL_RTX) - { - zero_mmx = reg; - emit_insn (gen_rtx_SET (reg, CONST0_RTX (mode))); - } - else - emit_move_insn (reg, zero_mmx); + emit_insn (gen_rtx_SET (reg, CONST0_RTX (mode))); } return true; } @@ -3800,11 +3793,6 @@ ix86_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) /* Now, generate instructions to zero all the other registers. */ - rtx zero_gpr = NULL_RTX; - rtx zero_vector = NULL_RTX; - rtx zero_mask = NULL_RTX; - rtx zero_mmx = NULL_RTX; - for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) { if (!TEST_HARD_REG_BIT (need_zeroed_hardregs, regno)) @@ -3815,59 +3803,34 @@ ix86_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) SET_HARD_REG_BIT (zeroed_hardregs, regno); - rtx reg, tmp, zero_rtx; machine_mode mode = zero_call_used_regno_mode (regno); - reg = gen_rtx_REG (mode, regno); - zero_rtx = CONST0_RTX (mode); + rtx reg = gen_rtx_REG (mode, regno); + rtx tmp = gen_rtx_SET (reg, CONST0_RTX (mode)); - if (mode == SImode) - if (zero_gpr == NULL_RTX) - { - zero_gpr = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - if (!TARGET_USE_MOV0 || optimize_insn_for_size_p ()) - { - rtx clob = gen_rtx_CLOBBER (VOIDmode, - gen_rtx_REG (CCmode, - FLAGS_REG)); - tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, - tmp, - clob)); - } - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_gpr); - else if (mode == V4SFmode) - if (zero_vector == NULL_RTX) - { - zero_vector = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_vector); - else if (mode == HImode) - if (zero_mask == NULL_RTX) - { - zero_mask = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_mask); - else if (mode == V4HImode) - if (zero_mmx == NULL_RTX) - { - zero_mmx = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_mmx); - else - gcc_unreachable (); + switch (mode) + { + case E_SImode: + if (!TARGET_USE_MOV0 || optimize_insn_for_size_p ()) + { + rtx clob = gen_rtx_CLOBBER (VOIDmode, + gen_rtx_REG (CCmode, + FLAGS_REG)); + tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, + tmp, + clob)); + } + /* FALLTHRU. */ + + case E_V4SFmode: + case E_HImode: + case E_V2SImode: + emit_insn (tmp); + break; + + default: + gcc_unreachable (); + } } return zeroed_hardregs; } diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c index 1ea6de880aa..818a56f1116 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */ void foo (void) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c index 389b1142264..01f6857fb56 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c @@ -11,11 +11,11 @@ foo (int x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c index 07d8de7c66f..4ed036e9f88 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=all -march=corei7 -msse" } */ void foo (void) @@ -7,15 +7,28 @@ foo (void) } /* { dg-final { scan-assembler-not "vzeroall" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 15 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm0, %xmm0" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm1, %xmm1" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm2, %xmm2" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm3, %xmm3" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm4, %xmm4" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm5, %xmm5" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm6, %xmm6" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm7, %xmm7" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm8, %xmm8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm9, %xmm9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm10, %xmm10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm11, %xmm11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm12, %xmm12" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm13, %xmm13" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm14, %xmm14" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm15, %xmm15" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c index 55a272cc53f..c361c0b3afd 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c @@ -9,11 +9,11 @@ foo (void) /* { dg-final { scan-assembler-times "vzeroall" 1 } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c index d0e975cb3d3..4d45fa56b2a 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -fno-stack-protector -fno-PIC" } */ extern void foo (void) __attribute__ ((zero_call_used_regs("used"))); diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c index d41a2557d10..fb5e6ddc1cd 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all" } */ +/* { dg-options "-O2 -fzero-call-used-regs=all -fno-stack-protector -fno-PIC" } */ extern void foo (void) __attribute__ ((zero_call_used_regs("skip"))); diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c index c79fcd39d7b..10cfa12f9ca 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used -fno-stack-protector" } */ int foo (int x) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c index 6f90723cc8e..0e399d4ebb0 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used -march=corei7 -fno-stack-protector -fno-PIC" } */ float foo (float z, float y, float x) @@ -9,5 +9,5 @@ foo (float z, float y, float x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm1, %xmm2" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm2, %xmm2" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c index 491d2d56774..cb0d5ebce04 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used -march=corei7 -fno-stack-protector -fno-PIC" } */ float foo (float z, float y, float x) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c index 52406fc70aa..cb93209a8ba 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c @@ -9,11 +9,11 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c index ccd491775c2..123bd05b51e 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=all -march=corei7 -msse" } */ float foo (float z, float y, float x) @@ -8,16 +8,28 @@ foo (float z, float y, float x) } /* { dg-final { scan-assembler-not "vzeroall" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" { target { ia32 } } } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm1, %xmm\[0-9\]+" 14 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm0, %xmm0" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm1, %xmm1" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm2, %xmm2" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm3, %xmm3" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm4, %xmm4" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm5, %xmm5" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm6, %xmm6" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm7, %xmm7" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm8, %xmm8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm9, %xmm9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm10, %xmm10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm11, %xmm11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm12, %xmm12" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm13, %xmm13" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm14, %xmm14" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm15, %xmm15" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c index b3570f318c1..e8c3d9b5f3d 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -march=corei7 -fno-stack-protector -fno-PIC" } */ __attribute__ ((zero_call_used_regs("used"))) float @@ -10,5 +10,5 @@ foo (float z, float y, float x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm1, %xmm2" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm2, %xmm2" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c index b25342065e9..63adbb9d356 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c @@ -11,11 +11,11 @@ foo (void) /* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c index 69d42d732fd..a3285bed8a0 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c @@ -11,19 +11,19 @@ foo (void) /* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler "kxorw\[ \t\]+%k0, %k0, %k0" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k2" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k3" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k4" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k5" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k6" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k7" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k1, %k1, %k1" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k2, %k2, %k2" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k3, %k3, %k3" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k4, %k4, %k4" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k5, %k5, %k5" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k6, %k6, %k6" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k7, %k7, %k7" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c index 8fb5299be56..3f22375d2fa 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c @@ -8,16 +8,16 @@ foo (int x) } /* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm1" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm2" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm3" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm4" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm5" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm6" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm7" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm0, %xmm0" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm1, %xmm1" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm2, %xmm2" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm3, %xmm3" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm4, %xmm4" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm5, %xmm5" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm6, %xmm6" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm7, %xmm7" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c index 26ceacf435d..b307d107319 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c @@ -8,8 +8,8 @@ foo (int x) } /* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c index 044e4af10f0..dfa8e01dc38 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c @@ -10,9 +10,9 @@ __v2si ret_mmx (void) } /* { dg-final { scan-assembler "pxor\[ \t\]+%mm1, %mm1" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm2" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm3" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm4" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm5" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm6" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm7" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm2, %mm2" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm3, %mm3" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm4, %mm4" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm5, %mm5" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm6, %mm6" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm7, %mm7" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c index 89e69b8ba72..6cd5c4cb067 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -fno-stack-protector" } */ void foo (void) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c index afa8b337b36..5a0e53110e6 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c @@ -10,5 +10,5 @@ __v2si ret_mmx (void) } /* { dg-final { scan-assembler "pxor\[ \t\]+%mm1, %mm1" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm2" } } */ -/* { dg-final { scan-assembler-not "movq\[ \t\]+%mm1, %mm\[34567\]" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm2, %mm2" } } */ +/* { dg-final { scan-assembler-not "pxor\[ \t\]+%mm\[34567\], %mm\[34567\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c index 1e98d17df7f..becc5b8b438 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -fno-stack-protector -fno-PIC" } */ extern void foo (void) __attribute__ ((zero_call_used_regs("used-gpr"))); diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c index 56aecdafad8..4367f96a859 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c @@ -10,11 +10,11 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c index fa831857ad8..88e3156b132 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all-gpr" } */ +/* { dg-options "-O2 -fzero-call-used-regs=all-gpr -fno-stack-protector" } */ extern void foo (void) __attribute__ ((zero_call_used_regs("skip"))); diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c index 0444a21f4da..460c301ec12 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used-gpr" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used-gpr -fno-stack-protector" } */ int foo (int x) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c index 75356db63c3..0eab76933f5 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c @@ -10,10 +10,10 @@ foo (int x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c index 64755b00c39..42dcaea4988 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -fno-stack-protector" } */ extern int foo (int) __attribute__ ((zero_call_used_regs("used-gpr"))); -- 2.27.0 [-- Attachment #3: 0001-i386-Adjust-fzero-call-used-regs-to-always-use-XOR-P.patch.gcc12 --] [-- Type: application/octet-stream, Size: 41612 bytes --] From aa26f1414eb9b6ebfee8663c0f0e03aebff2b2af Mon Sep 17 00:00:00 2001 From: Qing Zhao <qing.zhao@oracle.com> Date: Fri, 20 May 2022 14:44:49 +0000 Subject: [PATCH] i386: Adjust -fzero-call-used-regs to always use XOR [PR101891] Currently on i386, -fzero-call-used-regs uses a pattern of: XOR regA,regA MOV regA,regB MOV regA,regC ... RET However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). This patch will switch to always use XOR on i386: XOR regA,regA XOR regB,regB XOR regC,regC ... RET gcc/ChangeLog: PR target/101891 * config/i386/i386.cc (zero_call_used_regno_mode): use V2SImode as a generic MMX mode instead of V4HImode. (zero_all_mm_registers): Use SET to zero instead of MOV for zeroing scratch registers. (ix86_zero_call_used_regs): Likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector -fno-PIC. * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector -fno-PIC. * gcc.target/i386/zero-scratch-regs-16.c: Likewise. * gcc.target/i386/zero-scratch-regs-17.c: Likewise. * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector -fno-PIC, adjust mov to xor. * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector -fno-PIC. * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector -fno-PIC, Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-23.c: Likewise. * gcc.target/i386/zero-scratch-regs-26.c: Likewise. * gcc.target/i386/zero-scratch-regs-27.c: Likewise. * gcc.target/i386/zero-scratch-regs-28.c: Likewise. * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector -fno-PIC. * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. * gcc.target/i386/zero-scratch-regs-7.c: Likewise. * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. (cherry picked from commit 0b86943aca51175968e40bbb6f2662dfe3fbfe59) --- gcc/config/i386/i386.cc | 93 ++++++------------- .../gcc.target/i386/zero-scratch-regs-1.c | 2 +- .../gcc.target/i386/zero-scratch-regs-10.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-13.c | 37 +++++--- .../gcc.target/i386/zero-scratch-regs-14.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-15.c | 2 +- .../gcc.target/i386/zero-scratch-regs-16.c | 2 +- .../gcc.target/i386/zero-scratch-regs-17.c | 2 +- .../gcc.target/i386/zero-scratch-regs-18.c | 4 +- .../gcc.target/i386/zero-scratch-regs-19.c | 2 +- .../gcc.target/i386/zero-scratch-regs-2.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-20.c | 38 +++++--- .../gcc.target/i386/zero-scratch-regs-21.c | 4 +- .../gcc.target/i386/zero-scratch-regs-22.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-23.c | 30 +++--- .../gcc.target/i386/zero-scratch-regs-26.c | 26 +++--- .../gcc.target/i386/zero-scratch-regs-27.c | 10 +- .../gcc.target/i386/zero-scratch-regs-28.c | 12 +-- .../gcc.target/i386/zero-scratch-regs-3.c | 2 +- .../gcc.target/i386/zero-scratch-regs-31.c | 4 +- .../gcc.target/i386/zero-scratch-regs-4.c | 2 +- .../gcc.target/i386/zero-scratch-regs-5.c | 16 ++-- .../gcc.target/i386/zero-scratch-regs-6.c | 2 +- .../gcc.target/i386/zero-scratch-regs-7.c | 2 +- .../gcc.target/i386/zero-scratch-regs-8.c | 14 +-- .../gcc.target/i386/zero-scratch-regs-9.c | 2 +- 26 files changed, 180 insertions(+), 192 deletions(-) diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index b16df5b183e..86752a6516a 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -3706,7 +3706,7 @@ zero_call_used_regno_mode (const unsigned int regno) else if (MASK_REGNO_P (regno)) return HImode; else if (MMX_REGNO_P (regno)) - return V4HImode; + return V2SImode; else gcc_unreachable (); } @@ -3826,19 +3826,12 @@ zero_all_mm_registers (HARD_REG_SET need_zeroed_hardregs, if (!need_zero_all_mm) return false; - rtx zero_mmx = NULL_RTX; - machine_mode mode = V4HImode; + machine_mode mode = V2SImode; for (unsigned int regno = FIRST_MMX_REG; regno <= LAST_MMX_REG; regno++) if (regno != ret_mmx_regno) { rtx reg = gen_rtx_REG (mode, regno); - if (zero_mmx == NULL_RTX) - { - zero_mmx = reg; - emit_insn (gen_rtx_SET (reg, CONST0_RTX (mode))); - } - else - emit_move_insn (reg, zero_mmx); + emit_insn (gen_rtx_SET (reg, CONST0_RTX (mode))); } return true; } @@ -3908,11 +3901,6 @@ ix86_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) /* Now, generate instructions to zero all the other registers. */ - rtx zero_gpr = NULL_RTX; - rtx zero_vector = NULL_RTX; - rtx zero_mask = NULL_RTX; - rtx zero_mmx = NULL_RTX; - for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) { if (!TEST_HARD_REG_BIT (need_zeroed_hardregs, regno)) @@ -3923,59 +3911,34 @@ ix86_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) SET_HARD_REG_BIT (zeroed_hardregs, regno); - rtx reg, tmp, zero_rtx; machine_mode mode = zero_call_used_regno_mode (regno); - reg = gen_rtx_REG (mode, regno); - zero_rtx = CONST0_RTX (mode); + rtx reg = gen_rtx_REG (mode, regno); + rtx tmp = gen_rtx_SET (reg, CONST0_RTX (mode)); - if (mode == SImode) - if (zero_gpr == NULL_RTX) - { - zero_gpr = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - if (!TARGET_USE_MOV0 || optimize_insn_for_size_p ()) - { - rtx clob = gen_rtx_CLOBBER (VOIDmode, - gen_rtx_REG (CCmode, - FLAGS_REG)); - tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, - tmp, - clob)); - } - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_gpr); - else if (mode == V4SFmode) - if (zero_vector == NULL_RTX) - { - zero_vector = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_vector); - else if (mode == HImode) - if (zero_mask == NULL_RTX) - { - zero_mask = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_mask); - else if (mode == V4HImode) - if (zero_mmx == NULL_RTX) - { - zero_mmx = reg; - tmp = gen_rtx_SET (reg, zero_rtx); - emit_insn (tmp); - } - else - emit_move_insn (reg, zero_mmx); - else - gcc_unreachable (); + switch (mode) + { + case E_SImode: + if (!TARGET_USE_MOV0 || optimize_insn_for_size_p ()) + { + rtx clob = gen_rtx_CLOBBER (VOIDmode, + gen_rtx_REG (CCmode, + FLAGS_REG)); + tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, + tmp, + clob)); + } + /* FALLTHRU. */ + + case E_V4SFmode: + case E_HImode: + case E_V2SImode: + emit_insn (tmp); + break; + + default: + gcc_unreachable (); + } } return zeroed_hardregs; } diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c index 1ea6de880aa..818a56f1116 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */ void foo (void) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c index 389b1142264..01f6857fb56 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c @@ -11,11 +11,11 @@ foo (int x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[\t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c index 07d8de7c66f..4ed036e9f88 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=all -march=corei7 -msse" } */ void foo (void) @@ -7,15 +7,28 @@ foo (void) } /* { dg-final { scan-assembler-not "vzeroall" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 15 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm0, %xmm0" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm1, %xmm1" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm2, %xmm2" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm3, %xmm3" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm4, %xmm4" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm5, %xmm5" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm6, %xmm6" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm7, %xmm7" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm8, %xmm8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm9, %xmm9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm10, %xmm10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm11, %xmm11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm12, %xmm12" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm13, %xmm13" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm14, %xmm14" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm15, %xmm15" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c index 55a272cc53f..c361c0b3afd 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c @@ -9,11 +9,11 @@ foo (void) /* { dg-final { scan-assembler-times "vzeroall" 1 } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c index d0e975cb3d3..4d45fa56b2a 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -fno-stack-protector -fno-PIC" } */ extern void foo (void) __attribute__ ((zero_call_used_regs("used"))); diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c index d41a2557d10..fb5e6ddc1cd 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all" } */ +/* { dg-options "-O2 -fzero-call-used-regs=all -fno-stack-protector -fno-PIC" } */ extern void foo (void) __attribute__ ((zero_call_used_regs("skip"))); diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c index c79fcd39d7b..10cfa12f9ca 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used -fno-stack-protector" } */ int foo (int x) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c index 6f90723cc8e..0e399d4ebb0 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used -march=corei7 -fno-stack-protector -fno-PIC" } */ float foo (float z, float y, float x) @@ -9,5 +9,5 @@ foo (float z, float y, float x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm1, %xmm2" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm2, %xmm2" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c index 491d2d56774..cb0d5ebce04 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used -march=corei7 -fno-stack-protector -fno-PIC" } */ float foo (float z, float y, float x) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c index 52406fc70aa..cb93209a8ba 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c @@ -9,11 +9,11 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c index ccd491775c2..123bd05b51e 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=all -march=corei7 -msse" } */ float foo (float z, float y, float x) @@ -8,16 +8,28 @@ foo (float z, float y, float x) } /* { dg-final { scan-assembler-not "vzeroall" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" { target { ia32 } } } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm1, %xmm\[0-9\]+" 14 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm0, %xmm0" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm1, %xmm1" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm2, %xmm2" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm3, %xmm3" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm4, %xmm4" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm5, %xmm5" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm6, %xmm6" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm7, %xmm7" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm8, %xmm8" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm9, %xmm9" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm10, %xmm10" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm11, %xmm11" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm12, %xmm12" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm13, %xmm13" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm14, %xmm14" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm15, %xmm15" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c index b3570f318c1..e8c3d9b5f3d 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip -march=corei7" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -march=corei7 -fno-stack-protector -fno-PIC" } */ __attribute__ ((zero_call_used_regs("used"))) float @@ -10,5 +10,5 @@ foo (float z, float y, float x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm1, %xmm2" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm2, %xmm2" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c index b25342065e9..63adbb9d356 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c @@ -11,11 +11,11 @@ foo (void) /* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c index 69d42d732fd..a3285bed8a0 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c @@ -11,19 +11,19 @@ foo (void) /* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler "kxorw\[ \t\]+%k0, %k0, %k0" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k2" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k3" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k4" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k5" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k6" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k7" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k1, %k1, %k1" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k2, %k2, %k2" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k3, %k3, %k3" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k4, %k4, %k4" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k5, %k5, %k5" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k6, %k6, %k6" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k7, %k7, %k7" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c index 8fb5299be56..3f22375d2fa 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c @@ -8,16 +8,16 @@ foo (int x) } /* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm1" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm2" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm3" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm4" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm5" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm6" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm7" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm0, %xmm0" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm1, %xmm1" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm2, %xmm2" } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm3, %xmm3" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm4, %xmm4" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm5, %xmm5" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm6, %xmm6" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "\[a-z\]*xor\[a-z\]*\[ \t\]+%xmm7, %xmm7" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c index 26ceacf435d..b307d107319 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c @@ -8,8 +8,8 @@ foo (int x) } /* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c index 044e4af10f0..dfa8e01dc38 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c @@ -10,9 +10,9 @@ __v2si ret_mmx (void) } /* { dg-final { scan-assembler "pxor\[ \t\]+%mm1, %mm1" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm2" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm3" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm4" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm5" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm6" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm7" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm2, %mm2" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm3, %mm3" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm4, %mm4" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm5, %mm5" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm6, %mm6" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm7, %mm7" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c index 89e69b8ba72..6cd5c4cb067 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -fno-stack-protector" } */ void foo (void) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c index afa8b337b36..5a0e53110e6 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c @@ -10,5 +10,5 @@ __v2si ret_mmx (void) } /* { dg-final { scan-assembler "pxor\[ \t\]+%mm1, %mm1" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm2" } } */ -/* { dg-final { scan-assembler-not "movq\[ \t\]+%mm1, %mm\[34567\]" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm2, %mm2" } } */ +/* { dg-final { scan-assembler-not "pxor\[ \t\]+%mm\[34567\], %mm\[34567\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c index 1e98d17df7f..becc5b8b438 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -fno-stack-protector -fno-PIC" } */ extern void foo (void) __attribute__ ((zero_call_used_regs("used-gpr"))); diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c index 56aecdafad8..4367f96a859 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c @@ -10,11 +10,11 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c index fa831857ad8..88e3156b132 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all-gpr" } */ +/* { dg-options "-O2 -fzero-call-used-regs=all-gpr -fno-stack-protector" } */ extern void foo (void) __attribute__ ((zero_call_used_regs("skip"))); diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c index 0444a21f4da..460c301ec12 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=used-gpr" } */ +/* { dg-options "-O2 -fzero-call-used-regs=used-gpr -fno-stack-protector" } */ int foo (int x) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c index 75356db63c3..0eab76933f5 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c @@ -10,10 +10,10 @@ foo (int x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ /* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c index 64755b00c39..42dcaea4988 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=skip" } */ +/* { dg-options "-O2 -fzero-call-used-regs=skip -fno-stack-protector" } */ extern int foo (int) __attribute__ ((zero_call_used_regs("used-gpr"))); -- 2.27.0 ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: Back porting to GCC11/GCC12: Re: [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR 2022-05-23 15:16 ` Back porting to GCC11/GCC12: " Qing Zhao @ 2022-05-24 6:19 ` Richard Biener 2022-05-24 15:57 ` Qing Zhao 0 siblings, 1 reply; 12+ messages in thread From: Richard Biener @ 2022-05-24 6:19 UTC (permalink / raw) To: Qing Zhao; +Cc: Jakub Jelinek, gcc-patches Paul A Clarke via, kees Cook On Mon, 23 May 2022, Qing Zhao wrote: > Hi, > > I have added the patch to GCC11 and GCC12 in my local area and bootstrapped and regress tested on both x86 and aarch64, no any issues. > > Can I committed them to both GCC11 and GCC12 branches? Yes. Thanks, Richard. > Thanks. > > > > > > On May 10, 2022, at 8:38 AM, Qing Zhao via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > > > > > > >> On May 10, 2022, at 1:12 AM, Richard Biener <rguenther@suse.de> wrote: > >> > >> On Mon, 9 May 2022, Uros Bizjak wrote: > >> > >>> On Mon, May 9, 2022 at 5:44 PM Qing Zhao <qing.zhao@oracle.com> wrote: > >>>> > >>>> Another question: > >>>> > >>>> I think that this patch might need to be back ported to Gcc12 and GCC11. > >>>> > >>>> What?s your opinion on this? > >>> > >>> It is not a regression, so following general rules, the patch should > >>> not be backported. OTOH, the patch creates functionally equivalent > >>> code, better in some security aspects. The functionality is also > >>> hidden behind some non-default flag, so I think if release managers > >>> (CC'd) are OK with the backport, I'd give it a technical approval. > >>> > >>>> If so, when can I backport it? > >>> > >>> Let's keep it in the mainline for a week or two, before backporting it > >>> to non-EoL branches. > >> > >> OK from my POV after a week or two on trunk. > > > > Sure, I will do the back porting after two weeks. > > > > thanks. > > > > Qing > >> > >> Richard. > >> > >>> Uros. > >>> > >>>> > >>>> thanks. > >>>> > >>>> Qing > >>>> > >>>>> On May 7, 2022, at 4:06 AM, Uros Bizjak <ubizjak@gmail.com> wrote: > >>>>> > >>>>> On Fri, May 6, 2022 at 6:42 PM Qing Zhao <qing.zhao@oracle.com> wrote: > >>>>>> > >>>>>> > >>>>>> > >>>>>>> On May 6, 2022, at 10:58 AM, Uros Bizjak <ubizjak@gmail.com> wrote: > >>>>>>> > >>>>>>> On Fri, May 6, 2022 at 4:29 PM Qing Zhao <qing.zhao@oracle.com> wrote: > >>>>>>>> > >>>>>>>> Hi, > >>>>>>>> > >>>>>>>> As Kee?s requested in this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101891 > >>>>>>>> > >>>>>>>> ===== > >>>>>>>> > >>>>>>>> Currently -fzero-call-used-regs will use a pattern of: > >>>>>>>> > >>>>>>>> XOR regA,regA > >>>>>>>> MOV regA,regB > >>>>>>>> MOV regA,regC > >>>>>>>> ... > >>>>>>>> RET > >>>>>>>> > >>>>>>>> However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). > >>>>>>>> > >>>>>>>> Please switch to always using XOR: > >>>>>>>> > >>>>>>>> XOR regA,regA > >>>>>>>> XOR regB,regB > >>>>>>>> XOR regC,regC > >>>>>>>> ... > >>>>>>>> RET > >>>>>>>> > >>>>>>>> ======= > >>>>>>>> > >>>>>>>> This patch switch all MOV to XOR on i386. > >>>>>>>> > >>>>>>>> Bootstrapped and regresstion tested on x86_64-linux-gnu. > >>>>>>>> > >>>>>>>> Okay for gcc13? > >>>>>>>> > >>>>>>>> Thanks. > >>>>>>>> > >>>>>>>> Qing > >>>>>>>> > >>>>>>>> ========================================== > >>>>>>> > >>>>>>>> gcc/ChangeLog: > >>>>>>>> > >>>>>>>> * config/i386/i386.cc (zero_all_mm_registers): Use SET to zero instead > >>>>>>>> of MOV for zeroing scratch registers. > >>>>>>>> (ix86_zero_call_used_regs): Likewise. > >>>>>>>> > >>>>>>>> gcc/testsuite/ChangeLog: > >>>>>>>> > >>>>>>>> * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector > >>>>>>>> -fno-PIC. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector > >>>>>>>> -fno-PIC. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-16.c: Likewise. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-17.c: Likewise. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector > >>>>>>>> -fno-PIC, adjust mov to xor. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector > >>>>>>>> -fno-PIC. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector > >>>>>>>> -fno-PIC, Adjust mov to xor. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-23.c: Likewise. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-26.c: Likewise. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-27.c: Likewise. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-28.c: Likewise. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector > >>>>>>>> -fno-PIC. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-7.c: Likewise. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. > >>>>>>>> * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. > >>>>>>> > >>>>>>> Please use something like the attached (functionally equivalent) patch > >>>>>>> for the last hunk of your patch. > >>>>>> > >>>>>> Sure, I will update the code. > >>>>>>> > >>>>>>> Also, if possible, please use V2SImode as a generic MMX mode instead > >>>>>>> of V4HImode. > >>>>>> What?s the major purpose of this change? > >>>>> > >>>>> Although the generated code is the same, V2SI is used as a "generic" > >>>>> MMX move insn in the same way V2DI is used to describe generic SSE > >>>>> move instruction. > >>>>> > >>>>> Uros. > >>>> > >>> > >> > >> -- > >> Richard Biener <rguenther@suse.de> > >> SUSE Software Solutions Germany GmbH, Maxfeldstrasse 5, 90409 Nuernberg, > >> Germany; GF: Felix Imend > > -- Richard Biener <rguenther@suse.de> SUSE Software Solutions Germany GmbH, Maxfeldstrasse 5, 90409 Nuernberg, Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman; HRB 36809 (AG Nuernberg) ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: Back porting to GCC11/GCC12: Re: [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR 2022-05-24 6:19 ` Richard Biener @ 2022-05-24 15:57 ` Qing Zhao 0 siblings, 0 replies; 12+ messages in thread From: Qing Zhao @ 2022-05-24 15:57 UTC (permalink / raw) To: Richard Biener; +Cc: Jakub Jelinek, gcc-patches Paul A Clarke via, kees Cook Pushed to both gcc11 and gcc12. thanks. Qing > On May 24, 2022, at 1:19 AM, Richard Biener <rguenther@suse.de> wrote: > > On Mon, 23 May 2022, Qing Zhao wrote: > >> Hi, >> >> I have added the patch to GCC11 and GCC12 in my local area and bootstrapped and regress tested on both x86 and aarch64, no any issues. >> >> Can I committed them to both GCC11 and GCC12 branches? > > Yes. > > Thanks, > Richard. > >> Thanks. >> >> >> >> >>> On May 10, 2022, at 8:38 AM, Qing Zhao via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: >>> >>> >>> >>>> On May 10, 2022, at 1:12 AM, Richard Biener <rguenther@suse.de> wrote: >>>> >>>> On Mon, 9 May 2022, Uros Bizjak wrote: >>>> >>>>> On Mon, May 9, 2022 at 5:44 PM Qing Zhao <qing.zhao@oracle.com> wrote: >>>>>> >>>>>> Another question: >>>>>> >>>>>> I think that this patch might need to be back ported to Gcc12 and GCC11. >>>>>> >>>>>> What?s your opinion on this? >>>>> >>>>> It is not a regression, so following general rules, the patch should >>>>> not be backported. OTOH, the patch creates functionally equivalent >>>>> code, better in some security aspects. The functionality is also >>>>> hidden behind some non-default flag, so I think if release managers >>>>> (CC'd) are OK with the backport, I'd give it a technical approval. >>>>> >>>>>> If so, when can I backport it? >>>>> >>>>> Let's keep it in the mainline for a week or two, before backporting it >>>>> to non-EoL branches. >>>> >>>> OK from my POV after a week or two on trunk. >>> >>> Sure, I will do the back porting after two weeks. >>> >>> thanks. >>> >>> Qing >>>> >>>> Richard. >>>> >>>>> Uros. >>>>> >>>>>> >>>>>> thanks. >>>>>> >>>>>> Qing >>>>>> >>>>>>> On May 7, 2022, at 4:06 AM, Uros Bizjak <ubizjak@gmail.com> wrote: >>>>>>> >>>>>>> On Fri, May 6, 2022 at 6:42 PM Qing Zhao <qing.zhao@oracle.com> wrote: >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>>> On May 6, 2022, at 10:58 AM, Uros Bizjak <ubizjak@gmail.com> wrote: >>>>>>>>> >>>>>>>>> On Fri, May 6, 2022 at 4:29 PM Qing Zhao <qing.zhao@oracle.com> wrote: >>>>>>>>>> >>>>>>>>>> Hi, >>>>>>>>>> >>>>>>>>>> As Kee?s requested in this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101891 >>>>>>>>>> >>>>>>>>>> ===== >>>>>>>>>> >>>>>>>>>> Currently -fzero-call-used-regs will use a pattern of: >>>>>>>>>> >>>>>>>>>> XOR regA,regA >>>>>>>>>> MOV regA,regB >>>>>>>>>> MOV regA,regC >>>>>>>>>> ... >>>>>>>>>> RET >>>>>>>>>> >>>>>>>>>> However, this introduces both a register ordering dependency (e.g. the CPU cannot clear regB without clearing regA first), and while greatly reduces available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets at the end of functions (e.g. "MOV regA,regC; RET"). >>>>>>>>>> >>>>>>>>>> Please switch to always using XOR: >>>>>>>>>> >>>>>>>>>> XOR regA,regA >>>>>>>>>> XOR regB,regB >>>>>>>>>> XOR regC,regC >>>>>>>>>> ... >>>>>>>>>> RET >>>>>>>>>> >>>>>>>>>> ======= >>>>>>>>>> >>>>>>>>>> This patch switch all MOV to XOR on i386. >>>>>>>>>> >>>>>>>>>> Bootstrapped and regresstion tested on x86_64-linux-gnu. >>>>>>>>>> >>>>>>>>>> Okay for gcc13? >>>>>>>>>> >>>>>>>>>> Thanks. >>>>>>>>>> >>>>>>>>>> Qing >>>>>>>>>> >>>>>>>>>> ========================================== >>>>>>>>> >>>>>>>>>> gcc/ChangeLog: >>>>>>>>>> >>>>>>>>>> * config/i386/i386.cc (zero_all_mm_registers): Use SET to zero instead >>>>>>>>>> of MOV for zeroing scratch registers. >>>>>>>>>> (ix86_zero_call_used_regs): Likewise. >>>>>>>>>> >>>>>>>>>> gcc/testsuite/ChangeLog: >>>>>>>>>> >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector >>>>>>>>>> -fno-PIC. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-13.c: Add -msse. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector >>>>>>>>>> -fno-PIC. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-16.c: Likewise. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-17.c: Likewise. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector >>>>>>>>>> -fno-PIC, adjust mov to xor. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector >>>>>>>>>> -fno-PIC. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-20.c: Add -msse. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector >>>>>>>>>> -fno-PIC, Adjust mov to xor. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-23.c: Likewise. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-26.c: Likewise. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-27.c: Likewise. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-28.c: Likewise. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector >>>>>>>>>> -fno-PIC. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-7.c: Likewise. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor. >>>>>>>>>> * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector. >>>>>>>>> >>>>>>>>> Please use something like the attached (functionally equivalent) patch >>>>>>>>> for the last hunk of your patch. >>>>>>>> >>>>>>>> Sure, I will update the code. >>>>>>>>> >>>>>>>>> Also, if possible, please use V2SImode as a generic MMX mode instead >>>>>>>>> of V4HImode. >>>>>>>> What?s the major purpose of this change? >>>>>>> >>>>>>> Although the generated code is the same, V2SI is used as a "generic" >>>>>>> MMX move insn in the same way V2DI is used to describe generic SSE >>>>>>> move instruction. >>>>>>> >>>>>>> Uros. >>>>>> >>>>> >>>> >>>> -- >>>> Richard Biener <rguenther@suse.de> >>>> SUSE Software Solutions Germany GmbH, Maxfeldstrasse 5, 90409 Nuernberg, >>>> Germany; GF: Felix Imend >> >> > > -- > Richard Biener <rguenther@suse.de> > SUSE Software Solutions Germany GmbH, Maxfeldstrasse 5, 90409 Nuernberg, > Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman; > HRB 36809 (AG Nuernberg) ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-05-24 15:57 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-05-06 14:29 [patch][gcc13][i386][pr101891]Adjust -fzero-call-used-regs to always use XOR Qing Zhao 2022-05-06 15:58 ` Uros Bizjak 2022-05-06 16:42 ` Qing Zhao 2022-05-07 9:06 ` Uros Bizjak 2022-05-09 15:42 ` Qing Zhao 2022-05-09 15:44 ` Qing Zhao 2022-05-09 18:25 ` Uros Bizjak 2022-05-10 6:12 ` Richard Biener 2022-05-10 13:38 ` Qing Zhao 2022-05-23 15:16 ` Back porting to GCC11/GCC12: " Qing Zhao 2022-05-24 6:19 ` Richard Biener 2022-05-24 15:57 ` Qing Zhao
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