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[209.85.166.169]) by smtp.gmail.com with ESMTPSA id c10-20020a023b0a000000b0040f7db6a264sm6851412jaa.114.2023.04.29.10.22.05 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 29 Apr 2023 10:22:05 -0700 (PDT) Received: by mail-il1-f169.google.com with SMTP id e9e14a558f8ab-32a249b416fso8345965ab.1 for ; Sat, 29 Apr 2023 10:22:05 -0700 (PDT) X-Received: by 2002:a92:c104:0:b0:328:4ba7:f4d4 with SMTP id p4-20020a92c104000000b003284ba7f4d4mr6100312ile.8.1682788924912; Sat, 29 Apr 2023 10:22:04 -0700 (PDT) MIME-Version: 1.0 References: <20230428152102.1653600-1-pan2.li@intel.com> <2eeda95f-e645-6e73-7bc7-7b829a5bf70b@gmail.com> <72057d65-d5d4-00fc-307a-709ab0a82822@gmail.com> In-Reply-To: <72057d65-d5d4-00fc-307a-709ab0a82822@gmail.com> From: Andrew Waterman Date: Sat, 29 Apr 2023 10:21:53 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET To: Jeff Law Cc: "Li, Pan2" , "Wang, Yanzhang" , "gcc-patches@gcc.gnu.org" , "juzhe.zhong@rivai.ai" , "kito.cheng@sifive.com" Content-Type: multipart/alternative; boundary="00000000000019fe8d05fa7cd4aa" X-Spam-Status: No, score=-3.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000019fe8d05fa7cd4aa Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sat, Apr 29, 2023 at 8:06=E2=80=AFAM Jeff Law via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > > > > On 4/28/23 20:55, Li, Pan2 wrote: > > Thanks Jeff for comments. > > > > It makes sense to me. For the EQ operator we should have CONSTM1. > That's not the way I interpret the RVV documentation. Of course it's > not terribly clear. I guess one could do some experiments with qemu > or try to dig into the sail code and figure out the intent from those. > > > > Does this mean s390 parts has similar issue here? Then for instructions > like VMSEQ, we need to adjust the simplify_rtx up to a point. > You'd have to refer to the s390 instruction set reference to understand > precisely how the vector compares work. > > But as it stands this really isn't a simplify-rtx question, but a > question of the semantics of risc-v. What happens with the high bits > in the destination mask register is critical -- and if risc-v doesn't > set them to all ones in this case, then that would mean that defining > that macro is simply wrong for risc-v. The relevant statement in the spec is that "the tail elements are always updated with a tail-agnostic policy". The vmset.m instruction will cause mask register bits [0, vl-1] to be set to 1; elements [vl, VLMAX-1] will either be undisturbed or set to 1, i.e., effectively unspecified. > > jeff --00000000000019fe8d05fa7cd4aa--