From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x829.google.com (mail-qt1-x829.google.com [IPv6:2607:f8b0:4864:20::829]) by sourceware.org (Postfix) with ESMTPS id D70AD383FD73 for ; Fri, 16 Dec 2022 23:01:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D70AD383FD73 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-qt1-x829.google.com with SMTP id fu10so4010362qtb.0 for ; Fri, 16 Dec 2022 15:01:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=VC80SuQXAQIRqMZLgh793Gjj72Ib3h8Y2j80aGIIgSw=; b=k5tUm5xPS4nUyMxPpq0VwiDxYrYUtDGNtu+sXcqj7nOOX47IF5AWaW+HkcIlPAVjfn lvJ4qqL1KRzj3W7y+/2Oavu4bVl575xFPUwJh9mg0YG8H4aUqS8Qmx7mLwGCz+eCK6tx SfAcZVQppl83ccrlEiEzK/or2zgo2KK9bVap1knOy4/wEw7/qzxKFAb0TFoSqU9rtiMv v61eOt0G3qL+h+xux4mFuCvXyVHFLPJr8OIuGL1FdtB3f9cLZAOZK/aBbVDdG2FZfK+U h7tRaPv3+9c3Culvi7m0BR1HkgeMxXv9PztPLAHA1bw7k5Q3aVmt+K2zUHjfUdoLrebI EXjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=VC80SuQXAQIRqMZLgh793Gjj72Ib3h8Y2j80aGIIgSw=; b=sZCkS4pezY00nb7oMMraETawZcbgmRn/3Rori5XE+ANzsu2oZnaM2YHbcd9MlMCwgd nYkBxV0EzL2MxLeNObObOdAp4ofd/QNP3xfvunwnSv90UkXesfbZsfInIH2stU6kb0IJ dCevhQmmyXx+hREGw60TF+TzfCqtTJiAkdIRxaTvZKOKFw0yj2lq9MavHcb3z/DlWnpF wxChXF04dZvgXWMDOdhWfr7o1olQg0fHZtJ9ivn/xlwMn3T8RhSOhmN47S4FtA5B4kXW CW/mDdVd3qNwbqc8xogQyhOWS6zAeV2i/41OWFU8zLDrJ3eooMjEWmNUK+wK9Luabpuj enig== X-Gm-Message-State: AFqh2kq88pRPZECFZdkVUz+Wv1coHIeKizpLLcGpHSrRXd/m6wY5u6xo 8AgAoeW1wYCbBIgVG0+V6mKKnE0Km6M/6v7L6qCK5lIi2d0RrihvMTjvIheSLRzr7tSg6iHbQlI Z8VDCp356T4KBgeowaWSYeN0GbxgAkUOVuEkZBUaSp9+HecEvDlAAgvbAh1s98zvpMEU+wAA= X-Google-Smtp-Source: AMrXdXuN1TFinKTxfjXkF/gZPxomRSRPlnVPNmyroXVlJBy/V5tGVeuu/k5HwHVZ8rphJQv3RtmjLw== X-Received: by 2002:ac8:4250:0:b0:3a6:9c36:e3b1 with SMTP id r16-20020ac84250000000b003a69c36e3b1mr1749186qtm.42.1671231662553; Fri, 16 Dec 2022 15:01:02 -0800 (PST) Received: from mail-yb1-f181.google.com (mail-yb1-f181.google.com. [209.85.219.181]) by smtp.gmail.com with ESMTPSA id bj21-20020a05620a191500b006bb82221013sm2411510qkb.0.2022.12.16.15.01.01 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Dec 2022 15:01:01 -0800 (PST) Received: by mail-yb1-f181.google.com with SMTP id e141so3988131ybh.3 for ; Fri, 16 Dec 2022 15:01:01 -0800 (PST) X-Received: by 2002:a25:25c2:0:b0:706:ba81:7944 with SMTP id l185-20020a2525c2000000b00706ba817944mr10773042ybl.561.1671231661375; Fri, 16 Dec 2022 15:01:01 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Andrew Waterman Date: Fri, 16 Dec 2022 15:00:50 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] RISC-V: Remove unit-stride store from ta attribute To: Palmer Dabbelt Cc: jeffreyalaw@gmail.com, juzhe.zhong@rivai.ai, gcc-patches@gcc.gnu.org, Kito Cheng Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Dec 16, 2022 at 1:59 PM Palmer Dabbelt wrote: > > On Fri, 16 Dec 2022 12:01:04 PST (-0800), jeffreyalaw@gmail.com wrote: > > > > > > On 12/14/22 04:36, juzhe.zhong@rivai.ai wrote: > >> From: Ju-Zhe Zhong > >> > >> Since store instructions doesn't care about tail policy, we remove > >> vste from "ta" attribute. Hence, we could have more fusion chances > >> and better optimization. > >> > >> gcc/ChangeLog: > >> > >> * config/riscv/vector.md: Remove vste. > > Just to confirm that I understand the basic model. Vector stores only > > update active elements, thus they don't care about tail policy, right? > > > > Assuming that's the case, then this is OK. > > That had been my assumption as well, but I don't see that explicitly > called out in the ISA manual. I see > > Masked vector stores only update active memory elements. > > where "active" is defined as > > * The _body_ elements are those whose element index is greater than or equal > to the initial value in the `vstart` register, and less than the current > vector length setting in `vl`. The body can be split into two disjoint subsets: > > ** The _active_ elements during a vector instruction's execution are the > elements within the body and where the current mask is enabled at that element > position. The active elements can raise exceptions and update the destination > vector register group. > > but I don't see anything about the unmasked stores. The blurb about > tail elements only applies to registers groups, not memory addresses, so > I think that's kind of a grey area there too. I was pretty sure the intent > here was to have tail elements not updated in memory, so hopefully I'm just > missing something in the spec. As discussed on the github issue, I think there is sufficient justification in the spec to say that vector stores are forbidden from accessing tail elements even if unmasked. (And of course the ISA would be pretty useless if that weren't the case...) But there's no reason not to clarify the language in the spec, so as to make it easier for readers to grok. > > I open an issue to check: https://github.com/riscv/riscv-v-spec/issues/846