public inbox for gcc-patches@gcc.gnu.org
 help / color / mirror / Atom feed
From: Andrew Waterman <andrew@sifive.com>
To: Jeff Law <law@redhat.com>
Cc: Craig Blackmore <craig.blackmore@embecosm.com>,
	GCC Patches <gcc-patches@gcc.gnu.org>,
		Jim Wilson <jimw@sifive.com>,
	Ofer Shinaar <Ofer.Shinaar@wdc.com>,
	Nidal.Faour@wdc.com, 	Kito Cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v2 1/2] RISC-V: Add shorten_memrefs pass
Date: Sat, 26 Oct 2019 20:02:00 -0000	[thread overview]
Message-ID: <CA++6G0Bt-7+ViGdce7_KbiK=_627km+ZwBwWJnffuPaUapoj_A@mail.gmail.com> (raw)
In-Reply-To: <aecb2aea-793c-ec75-2328-271ec2acbf8c@redhat.com>

I don't know enough to say whether the legitimize_address hook is
sufficient for the intended purpose, but I am sure that RISC-V's
concerns are not unique: other GCC targets have to cope with
offset-size constraints that are coupled to register-allocation
constraints.


On Sat, Oct 26, 2019 at 11:21 AM Jeff Law <law@redhat.com> wrote:
>
> On 10/25/19 11:39 AM, Craig Blackmore wrote:
> > This patch aims to allow more load/store instructions to be compressed by
> > replacing a load/store of 'base register + large offset' with a new load/store
> > of 'new base + small offset'. If the new base gets stored in a compressed
> > register, then the new load/store can be compressed. Since there is an overhead
> > in creating the new base, this change is only attempted when 'base register' is
> > referenced in at least 4 load/stores in a basic block.
> >
> > The optimization is implemented in a new RISC-V specific pass called
> > shorten_memrefs which is enabled for RVC targets. It has been developed for the
> > 32-bit lw/sw instructions but could also be extended to 64-bit ld/sd in future.
> >
> > Tested on bare metal rv32i, rv32iac, rv32im, rv32imac, rv32imafc, rv64imac,
> > rv64imafdc via QEMU. No regressions.
> >
> > gcc/ChangeLog:
> >
> >       * config.gcc: Add riscv-shorten-memrefs.o to extra_objs for riscv.
> >       * config/riscv/riscv-passes.def: New file.
> >       * config/riscv/riscv-protos.h (make_pass_shorten_memrefs): Declare.
> >       * config/riscv/riscv-shorten-memrefs.c: New file.
> >       * config/riscv/riscv.c (tree-pass.h): New include.
> >       (riscv_compressed_reg_p): New Function
> >       (riscv_compressed_lw_offset_p): Likewise.
> >       (riscv_compressed_lw_address_p): Likewise.
> >       (riscv_shorten_lw_offset): Likewise.
> >       (riscv_legitimize_address): Attempt to convert base + large_offset
> >         to compressible new_base + small_offset.
> >       (riscv_address_cost): Make anticipated compressed load/stores
> >         cheaper for code size than uncompressed load/stores.
> >       (riscv_register_priority): Move compressed register check to
> >         riscv_compressed_reg_p.
> >       * config/riscv/riscv.h (RISCV_MAX_COMPRESSED_LW_OFFSET): Define.
> >       * config/riscv/riscv.opt (mshorten-memefs): New option.
> >       * config/riscv/t-riscv (riscv-shorten-memrefs.o): New rule.
> >       (PASSES_EXTRA): Add riscv-passes.def.
> >       * doc/invoke.texi: Document -mshorten-memrefs.
> This has traditionally been done via the the legitimize_address hook.
> Is there some reason that hook is insufficient for this case?
>
> The hook, IIRC, is called out explow.c.
>
> Jeff
>

  parent reply	other threads:[~2019-10-26 19:33 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-12 16:19 [PATCH] RISC-V: Allow more load/stores to be compressed Craig Blackmore
2019-09-18 10:01 ` Kito Cheng
2019-10-25 17:40   ` [PATCH v2 0/2] " Craig Blackmore
2019-10-25 17:40     ` [PATCH v2 1/2] RISC-V: Add shorten_memrefs pass Craig Blackmore
2019-10-26 18:25       ` Jeff Law
2019-10-26 19:16         ` Oleg Endo
2019-10-26 20:04           ` Jeff Law
2019-10-26 20:02         ` Andrew Waterman [this message]
2019-10-26 20:16           ` Jeff Law
2019-10-27  7:13             ` Oleg Endo
2019-10-31  0:00       ` Jim Wilson
2019-10-31  9:42         ` Nidal Faour
2019-10-31 10:42           ` Andrew Waterman
2019-10-31 15:57             ` Ofer Shinaar
2019-12-10 18:28         ` Craig Blackmore
2020-02-19 11:40           ` Craig Blackmore
2020-04-08 16:04             ` Jim Wilson
2020-04-27 17:08               ` Craig Blackmore
2020-05-12 22:33                 ` Jim Wilson
2020-05-13 17:51                   ` Craig Blackmore
2019-10-31  0:03       ` Jim Wilson
2019-10-25 17:57     ` [PATCH v2 2/2] sched-deps.c: Avoid replacing address if it increases address cost Craig Blackmore
2019-10-31  2:00       ` Jim Wilson
2019-12-10 18:29         ` Craig Blackmore

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CA++6G0Bt-7+ViGdce7_KbiK=_627km+ZwBwWJnffuPaUapoj_A@mail.gmail.com' \
    --to=andrew@sifive.com \
    --cc=Nidal.Faour@wdc.com \
    --cc=Ofer.Shinaar@wdc.com \
    --cc=craig.blackmore@embecosm.com \
    --cc=gcc-patches@gcc.gnu.org \
    --cc=jimw@sifive.com \
    --cc=kito.cheng@gmail.com \
    --cc=law@redhat.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).