Re: RISC-V: Replace not + bitwise_imm with li + bitwise_not

[Andrew Waterman <andrew@sifive.com>]

Note this is a size-speed tradeoff, as the Zcb extension has a
16-bit-wide C.NOT instruction.  Might want to suppress this
optimization when Zcb is present and the function is being optimized
for size.


On Mon, Sep 11, 2023 at 9:52 AM Jivan Hakobyan via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> In the case when we have C code like this
>
> int foo (int a) {
>    return 100 & ~a;
> }
>
> GCC generates the following instruction sequence
>
> foo:
>      not     a0,a0
>      andi    a0,a0,100
>      ret
>
> This patch replaces that with this sequence
> foo:
>      li a5,100
>      andn a0,a5,a0
>      ret
>
> The profitability comes from an out-of-order processor being able to
> issue the "li a5, 100" at any time after it's fetched while "not a0, a0" has
> to wait until any prior setter of a0 has reached completion.
>
>
> gcc/ChangeLog:
>         * config/riscv/bitmanip.md (*<optab>_not_const<mode>): New split
> pattern.
>
> gcc/testsuite/ChangeLog:
>         * gcc.target/riscv/zbb-andn-orn-01.c: New test.
>         * gcc.target/riscv/zbb-andn-orn-02.c: Likewise.
>
>
> --
> With the best regards
> Jivan Hakobyan