From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by sourceware.org (Postfix) with ESMTPS id A0AA03858C00 for ; Thu, 23 Feb 2023 21:24:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A0AA03858C00 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pf1-x434.google.com with SMTP id a26so6730882pfo.9 for ; Thu, 23 Feb 2023 13:24:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=3QhlOKDY55ky84FEB9dd/qAnXjT1bHe4RPVX94v1ffk=; b=i+r8BQfLmeKTp5GvElimdF9KhKWu1RryAHkn87V24QdYU9W6qM3qYDHhs0Lic5CVCL AtvQxT5DF5MR7iWVgO0hplwsz5Mpa7lrCWF+FTedJpRl8IIMw1ArUQc+yqhib5zqhGg9 XRDv7/JBz/+Qdhx4qDjbwGXRFOHCb13W6+vpcmrV+zLPCE6+Bb2uYCHUBAIu34frRKzd 6TvrtkWIUDvvP3aVDXzrjzD8RpWw/MIdAEm9iwFjrk+mXQwi9JUCectGbHYMlKDwTJeS heTk5Z3sA6IMfApoU5GBncCviNu5lowbMovewCd/hJRDpBv1Fk+ab3mFvOtl8HMbvd6f y7sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=3QhlOKDY55ky84FEB9dd/qAnXjT1bHe4RPVX94v1ffk=; b=cH+PxwQXtLbjwWA42eYVotqZndEjoYWokohsmnblgYmaByXUReQVBfoNPujCWwyQDW LaiyWJmiEQxzaPUawfFFMV5Htkahyd1dk1Jl0cl9LhzFEVESovfH/mxrYH+4UXhWKs9U f5fpg2JzUsg5DOLR3fjfTOS/sKBt4qavBvJDDkUHOITMlKsg8nj2ZChglerf9w/hOwaY 290o8YrYVSKbRPkteE/VI/gchzF89hyUMssWWtwfsWq6dLsM/c6Jw37wQy9Ou7tnvlcN 1+3EP5zuAdgg+tKZ0FHWG5SuSl8lS1MpjNd332dI7x8leCSn2woxBQEbi5M6CMpRSyR4 GaRg== X-Gm-Message-State: AO0yUKVVsR+vfq364VQgEKSVA5jw6uAbm/KrCBCLtZT/Yy5T2q7CRcje QiU/vAh+gdd6EJxDV4Xk70R4AmAeExqOBKlObzg= X-Google-Smtp-Source: AK7set8zeGHReMNihqn1DBiI8LXNehDIPTgR69E76aykRGuhBsP5UwpyjUHoBPLqurZXgLH8fP1X3gbEMXvvOWdA9HM= X-Received: by 2002:a05:6a00:2a6:b0:593:fcfb:208b with SMTP id q6-20020a056a0002a600b00593fcfb208bmr2182902pfs.3.1677187444263; Thu, 23 Feb 2023 13:24:04 -0800 (PST) MIME-Version: 1.0 References: <20221209182510.43515-1-rzinsly@ventanamicro.com> In-Reply-To: <20221209182510.43515-1-rzinsly@ventanamicro.com> From: Andrew Pinski Date: Thu, 23 Feb 2023 13:23:52 -0800 Message-ID: Subject: Re: [PATCH v2] RISC-V: Produce better code with complex constants [PR95632] [PR106602] To: Raphael Moreira Zinsly Cc: gcc-patches@gcc.gnu.org, jlaw@ventanamicro.com, jakub@redhat.com, palmer@dabbelt.com, philipp.tomsich@vrull.eu Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Dec 9, 2022 at 10:25 AM Raphael Moreira Zinsly wrote: > > Changes since v1: > - Fixed formatting issues. > - Added a name to the define_insn_and_split pattern. > - Set the target on the 'dg-do compile' in pr106602.c. > - Removed the rv32 restriction in pr95632.c. > > -- >8 -- > > Due to RISC-V limitations on operations with big constants combine > is failing to match such operations and is not being able to > produce optimal code as it keeps splitting them. By pretending we > can do those operations we can get more opportunities for > simplification of surrounding instructions. > > 2022-12-06 Raphael Moreira Zinsly > Jeff Law > > gcc/Changelog: > PR target/95632 > PR target/106602 > * config/riscv/riscv.md: New pattern to simulate complex > const_int loads. > > gcc/testsuite/ChangeLog: > * gcc.target/riscv/pr95632.c: New test. > * gcc.target/riscv/pr106602.c: New test. > --- > gcc/config/riscv/riscv.md | 15 +++++++++++++++ > gcc/testsuite/gcc.target/riscv/pr106602.c | 14 ++++++++++++++ > gcc/testsuite/gcc.target/riscv/pr95632.c | 15 +++++++++++++++ > 3 files changed, 44 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602.c > create mode 100644 gcc/testsuite/gcc.target/riscv/pr95632.c > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index df57e2b0b4a..b0daa4b19eb 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -1667,6 +1667,21 @@ > MAX_MACHINE_MODE, &operands[3], TRUE); > }) > > +;; Pretend to have the ability to load complex const_int in order to get > +;; better code generation around them. > +(define_insn_and_split "*mvconst_internal" > + [(set (match_operand:GPR 0 "register_operand" "=r") > + (match_operand:GPR 1 "splittable_const_int_operand" "i"))] > + "cse_not_expected" This is just way broken. This should be combined with the normal move instructions and just be a define_split. See PR 108892 for a testcase which shows this breaking how the register allocator thinks it should work. Thanks, Andrew > + "#" > + "&& 1" > + [(const_int 0)] > +{ > + riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]), > + mode, TRUE); > + DONE; > +}) > + > ;; 64-bit integer moves > > (define_expand "movdi" > diff --git a/gcc/testsuite/gcc.target/riscv/pr106602.c b/gcc/testsuite/gcc.target/riscv/pr106602.c > new file mode 100644 > index 00000000000..825b1a143b5 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr106602.c > @@ -0,0 +1,14 @@ > +/* { dg-do compile { target { riscv64*-*-* } } } */ > +/* { dg-options "-O2" } */ > + > +unsigned long > +foo2 (unsigned long a) > +{ > + return (unsigned long)(unsigned int) a << 6; > +} > + > +/* { dg-final { scan-assembler-times "slli\t" 1 } } */ > +/* { dg-final { scan-assembler-times "srli\t" 1 } } */ > +/* { dg-final { scan-assembler-not "\tli\t" } } */ > +/* { dg-final { scan-assembler-not "addi\t" } } */ > +/* { dg-final { scan-assembler-not "and\t" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/pr95632.c b/gcc/testsuite/gcc.target/riscv/pr95632.c > new file mode 100644 > index 00000000000..b865c2f2e97 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr95632.c > @@ -0,0 +1,15 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2" } */ > + > +unsigned short > +foo (unsigned short crc) > +{ > + crc ^= 0x4002; > + crc >>= 1; > + crc |= 0x8000; > + > + return crc; > +} > + > +/* { dg-final { scan-assembler-times "srli\t" 1 } } */ > +/* { dg-final { scan-assembler-not "slli\t" } } */ > -- > 2.38.1 >