From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 98935 invoked by alias); 20 Jun 2017 05:06:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 98534 invoked by uid 89); 20 Jun 2017 05:06:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=person X-HELO: mail-yw0-f178.google.com Received: from mail-yw0-f178.google.com (HELO mail-yw0-f178.google.com) (209.85.161.178) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 20 Jun 2017 05:06:26 +0000 Received: by mail-yw0-f178.google.com with SMTP id l75so48046695ywc.3 for ; Mon, 19 Jun 2017 22:06:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=WZgzWXH6Ar2Ne2bPZ9dlxDyUYOx/EwGz4EDqhogs9A0=; b=WE7d2reP+KjwtoJszdSR9ZYzfr0fqEMSzMxhrn4mkqTgVpoHIKb5X/+Bjy2FPCfBUg kcWQLwtSejC/7ecH/WfC+Kq8uVbDYYmJJNXHx+e0sqMZKzs8RS/H/cfHNrHQzBnsKMdf M9LY7E+/gnAeBnMAiVKsoMytPgaoRXs8z/2OweZJyHhrwgNQeyicQ8vo0d00T+Bw5krL UU06mnh4uJv3n7qClLnw6iML1ELJD7U6ryChw+8U+Nai8ExWp5jwB80Qibr5jRuGaV8j YtrWfVqDaLni4sNW/xwZIEz2hgKtoDE2oewiUYg0JlHIWeP8od43jfsn240cYz5Qpku1 QeSA== X-Gm-Message-State: AKS2vOzsSjyBFr7EoXvGTdVdFbpmTD7IzvR3ST5ErXSx48pMgcxqDy9i lZ2X8+wd/c00v4My2NCTu3G1JA0U9A== X-Received: by 10.129.130.71 with SMTP id s68mr22239549ywf.42.1497935184981; Mon, 19 Jun 2017 22:06:24 -0700 (PDT) MIME-Version: 1.0 Received: by 10.129.47.200 with HTTP; Mon, 19 Jun 2017 22:06:24 -0700 (PDT) In-Reply-To: <58B56D3E.3090704@foss.arm.com> References: <58B56D3E.3090704@foss.arm.com> From: Andrew Pinski Date: Tue, 20 Jun 2017 05:06:00 -0000 Message-ID: Subject: Re: [PATCH][AArch64] Allow const0_rtx operand for atomic compare-exchange patterns To: Kyrill Tkachov Cc: GCC Patches , Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2017-06/txt/msg01391.txt.bz2 On Tue, Feb 28, 2017 at 4:29 AM, Kyrill Tkachov wrote: > Hi all, > > For the testcase in this patch we currently generate: > foo: > mov w1, 0 > ldaxr w2, [x0] > cmp w2, 3 > bne .L2 > stxr w3, w1, [x0] > cmp w3, 0 > .L2: > cset w0, eq > ret > > Note that the STXR could have been storing the WZR register instead of > moving zero into w1. > This is due to overly strict predicates and constraints in the store > exclusive pattern and the > atomic compare exchange expanders and splitters. > This simple patch fixes that in the patterns concerned and with it we can > generate: > foo: > ldaxr w1, [x0] > cmp w1, 3 > bne .L2 > stxr w2, wzr, [x0] > cmp w2, 0 > .L2: > cset w0, eq > ret > > > Bootstrapped and tested on aarch64-none-linux-gnu. > Ok for GCC 8? This patch broke compiling with -march=+lse ./home/apinski/src/local5/gcc/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c:9:1: error: unrecognizable insn: } ^ (insn 6 3 7 2 (parallel [ (set (reg:CC 66 cc) (unspec_volatile:CC [ (const_int 0 [0]) ] UNSPECV_ATOMIC_CMPSW)) (set (reg:SI 78) (mem/v:SI (reg/v/f:DI 77 [ a ]) [-1 S4 A32])) (set (mem/v:SI (reg/v/f:DI 77 [ a ]) [-1 S4 A32]) (unspec_volatile:SI [ (const_int 3 [0x3]) (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 2 [0x2]) ] UNSPECV_ATOMIC_CMPSW)) ]) "/home/apinski/src/local5/gcc/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c":8 -1 (nil)) during RTL pass: vregs Note also your new testcase is broken even for defaulting to +lse as it is not going to match stxr. I might be the only person who tests +lse by default :). Thanks, Andrew Pinski > > Thanks, > Kyrill > > 2017-02-28 Kyrylo Tkachov > > * config/aarch64/atomics.md (atomic_compare_and_swap expander): > Use aarch64_reg_or_zero predicate for operand 4. > (aarch64_compare_and_swap define_insn_and_split): > Use aarch64_reg_or_zero predicate for operand 3. Add 'Z' constraint. > (aarch64_store_exclusive): Likewise for operand 2. > > 2017-02-28 Kyrylo Tkachov > > * gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: New test.