From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by sourceware.org (Postfix) with ESMTPS id B727D3858D1E for ; Tue, 23 May 2023 02:38:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B727D3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-253520adb30so4128892a91.1 for ; Mon, 22 May 2023 19:38:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684809487; x=1687401487; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=mMDK3vvXNUyMx6s1M4shF9CI7qrBSe2yzLXRU9FK1GA=; b=goRPpIckJLJ+2Bq1ZjyyShchFUCeuwnAqiejcV3xwHkbHtivKY2ARH0xLykK4Mp3AY urx766GhR5MY34tzuWDIRpe2dVx2SnnlDfMpK/gBU7qtOBPYZeu5u/hlLnvAqarRsUbP wZmHunk+V1CdLLY3PCPN//SAFZN7PT0ashOw7auPXe+laI1dXk5IGRdbLBauL1ScUy7k 5xx39W0TRMhdsSzALKIXp98GJvaSXaosPNCl5ILQkogCPUHFYGpVlkc9x8PPYEwpdQRb v97uUkQ8bIepU+GTbOkhc8ngQEQBoEws5cM/58j1OMaTYXY0C8QP4xZ6DT/1gKWGXOfO WGRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684809487; x=1687401487; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mMDK3vvXNUyMx6s1M4shF9CI7qrBSe2yzLXRU9FK1GA=; b=cZRHSCMf5YhuUJjS550jCLarG2Bnoy68hMO5F6yfOZbrvjgN1Jtjj7LLng1TLhg52K gKpz28m98mERsngBPuixr1K4+ZJtjh4cHD74WQYWtDY3BccoFEkWdm0zNkkxVw+4CAK7 OVUAYwLkd57kC1frHAING6wjzwwghu6o+NCVwfZdk1m0BNkIJAFYVto3FUTqEzxwWIjN ux7YyGUwVuOupK6/WMjA6FzDEh7r/8SIHsQsnG1kTy/XOfWKkZlays099Nh0MiYiDpCg xtrBWfqB2aUexq4hkPiyCWauFGK5R0hAEqufYFykdRKo2YYvh/sI8XSWJ8t75jTD/jgA rpzQ== X-Gm-Message-State: AC+VfDwxgktgZ7EcaJxTHyxNILVJIk04qh9qHazZk6C2w4pJQNkdRQ4j +rLAJZmXb6gLm+vgPgHsaACvrgVDfOFVnynfS/s= X-Google-Smtp-Source: ACHHUZ5NVdXW4jH7kQHPZXB2bJl/BSZBvOOahxAX4vEg51UeGtwYtS3nnWgzJjK4wwbmgSJ5ZwbLF5ehycZVaY5YUaw= X-Received: by 2002:a17:90a:d188:b0:253:4212:9157 with SMTP id fu8-20020a17090ad18800b0025342129157mr13208435pjb.28.1684809487080; Mon, 22 May 2023 19:38:07 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Andrew Pinski Date: Mon, 22 May 2023 19:37:54 -0700 Message-ID: Subject: Re: [PATCH 1/2] xtensa: Optimize '(x & CST1_POW2) != 0 ? CST2_POW2 : 0' To: Max Filippov Cc: "Takayuki 'January June' Suwa" , GCC Patches Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,PLING_QUERY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, May 22, 2023 at 7:28=E2=80=AFPM Max Filippov via Gcc-patches wrote: > > Hi Suwa-san, > > On Mon, May 22, 2023 at 12:06=E2=80=AFAM Takayuki 'January June' Suwa > wrote: > > > > This patch decreses one machine instruction from "single bit extraction > > with shifting" operation, and tries to eliminate the conditional > > branch if CST2_POW2 doesn't fit into signed 12 bits with the help > > of ifcvt optimization. > > > > /* example #1 */ > > int test0(int x) { > > return (x & 1048576) !=3D 0 ? 1024 : 0; > > } > > extern int foo(void); > > int test1(void) { > > return (foo() & 1048576) !=3D 0 ? 16777216 : 0; > > } > > > > ;; before > > test0: > > movi a9, 0x400 > > srai a2, a2, 10 > > and a2, a2, a9 > > ret.n > > test1: > > addi sp, sp, -16 > > s32i.n a0, sp, 12 > > call0 foo > > extui a2, a2, 20, 1 > > slli a2, a2, 20 > > beqz.n a2, .L2 > > movi.n a2, 1 > > slli a2, a2, 24 > > .L2: > > l32i.n a0, sp, 12 > > addi sp, sp, 16 > > ret.n > > > > ;; after > > test0: > > extui a2, a2, 20, 1 > > slli a2, a2, 10 > > ret.n > > test1: > > addi sp, sp, -16 > > s32i.n a0, sp, 12 > > call0 foo > > l32i.n a0, sp, 12 > > extui a2, a2, 20, 1 > > slli a2, a2, 24 > > addi sp, sp, 16 > > ret.n > > > > In addition, if the left shift amount ('exact_log2(CST2_POW2)') is > > between 1 through 3 and a either addition or subtraction with another > > register follows, emit a ADDX[248] or SUBX[248] machine instruction > > instead of separate left shift and add/subtract ones. > > > > /* example #2 */ > > int test2(int x, int y) { > > return ((x & 1048576) !=3D 0 ? 4 : 0) + y; > > } > > int test3(int x, int y) { > > return ((x & 2) !=3D 0 ? 8 : 0) - y; > > } > > > > ;; before > > test2: > > movi.n a9, 4 > > srai a2, a2, 18 > > and a2, a2, a9 > > add.n a2, a2, a3 > > ret.n > > test3: > > movi.n a9, 8 > > slli a2, a2, 2 > > and a2, a2, a9 > > sub a2, a2, a3 > > ret.n > > > > ;; after > > test2: > > extui a2, a2, 20, 1 > > addx4 a2, a2, a3 > > ret.n > > test3: > > extui a2, a2, 1, 1 > > subx8 a2, a2, a3 > > ret.n > > > > gcc/ChangeLog: > > > > * config/xtensa/predicates.md (addsub_operator): New. > > * config/xtensa/xtensa.md (*extzvsi-1bit_ashlsi3, > > *extzvsi-1bit_addsubx): New insn_and_split patterns. > > * config/xtensa/xtensa.cc (xtensa_rtx_costs): > > Add a special case about ifcvt 'noce_try_cmove()' to handle > > constant loads that do not fit into signed 12 bits in the > > patterns added above. > > --- > > gcc/config/xtensa/predicates.md | 3 ++ > > gcc/config/xtensa/xtensa.cc | 3 +- > > gcc/config/xtensa/xtensa.md | 75 +++++++++++++++++++++++++++++++++ > > 3 files changed, 80 insertions(+), 1 deletion(-) > > This change introduces a bunch of test failures on big endian configurati= on. > I believe that's because the starting bit position for zero_extract is co= unted > from different ends depending on the endianness. Yes I ran into something similar just recently when I was improving a similar thing in expand. Thanks, Andrew > > -- > Thanks. > -- Max