From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf34.google.com (mail-qv1-xf34.google.com [IPv6:2607:f8b0:4864:20::f34]) by sourceware.org (Postfix) with ESMTPS id F15163858D3C; Sun, 24 Dec 2023 09:29:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F15163858D3C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F15163858D3C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::f34 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703410154; cv=none; b=nRPMxr/lDTk9jjMYoHMJHfhM7C8uXhTJRAita6DGGbG/VElZR+B267K5NGwrMkZK6v92pL4wMfEGZty4hSkJhLbxpLfYfVo8qXWENJaPCyWpD3n80SeF7ULTSNyA1SQxVhYQ2GVQ0gOnSXuU0EcEaT3iFu61K3SblxaP5ZNTdxw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703410154; c=relaxed/simple; bh=EHdYnEqrJ27TeJhMnfml9amHC13/W4qnw3T2q2m176o=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=ZBWPFkVC45HhsJ902cKhPEdCGJ4OJq5jqw8fYjnoyNS3d/o7UNguCdb575/Pccv8TdIaalh2tepOWmvExIg64GdSsPwUqXwp4Og1tjQ7ujKIKIDDLAyyTN2d3h6Vr6UvbuojX2MNtrqM3pjA8XAfSOpj+gyyZDR8klMbnilrgis= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-qv1-xf34.google.com with SMTP id 6a1803df08f44-67f645f2e3fso25416936d6.1; Sun, 24 Dec 2023 01:29:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703410147; x=1704014947; darn=gcc.gnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Z/0CmsIe5hajbV7eiqByE2vDsiAPYExTSQFe7jpAAc8=; b=Milsn0NZCBk5O033yUyJVyvAzp5lv0jfMlMei7k0x1waMnnjvpZBwliDErDFcpVzQm Po7or1qJBMLER+36aD3u4UaQazxf1pItzzJ3H4L7HbnkFa5Yp26UuqXct1E86rK8DOV7 gn+P3c9LubEE5rSFugY0sI5Jsp3I6igAjhtTNAp7Os+4VjMBBYrxuYcRXKEtOEaQbNcZ NpfJNa3JYK0auhPeLf2UvccF6HExZdQaF4aLZ5B+7sXOi0AVdqR8IzsjivbKKPNkZF0f rncJEp9rn8T44zXg7c9uSNQ9gIc3eUn4Y493Iyxq0q7FGYdAzddSQ8jzW96Thb1Kah3i YIZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703410147; x=1704014947; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Z/0CmsIe5hajbV7eiqByE2vDsiAPYExTSQFe7jpAAc8=; b=kSl77OY9072HvBch77eXeppKJ9sV4nyFsh12QIeUPC5tN88ubyMZG0XqAEk1hIF9Rr PGwdFDqakdSsJsUMWOwDWVnCfKWfG9ER9SIII/nGga9oifwHdcUMey1L4JuGgh9gau4m uRRPN4yUMBldxv/m+wuTyk/KenjwJGJV0LsY3IFPdbKsK/9Jr+c5jw7cOP8cuL6nAnbC 1VTQ5AaIHhB5JV/ZiRdQSpSZ0POxM3AgFZGpaSR5iiR6G8P2daBSp0KLhOXoyr0Bmr9f WUlVW7jgUc8LaeKvF7BSjvpY8ttbefGSj8Q+LyAtAQhhTfyglJhq1ReJYjaA5sLMsnBG 2SGw== X-Gm-Message-State: AOJu0YyG468RlkpQ0NRGXl9UwqGnCB9Z7+x5tVolnDmYrlUVu7vgKpKz U3MDsY/MFIjPEyBshb7Kpf0Fuga8s66f1LP+A6D3cppw X-Google-Smtp-Source: AGHT+IHtcpX4mRGTW+ln4oQKK5k+Idf3ocQ3phK6ilTEoRRVYwgSapP0OReHmSb/S0JU36fbTs09ecVBGV+GtWo+j70= X-Received: by 2002:a05:622a:316:b0:425:4043:1da8 with SMTP id q22-20020a05622a031600b0042540431da8mr5591331qtw.123.1703410146773; Sun, 24 Dec 2023 01:29:06 -0800 (PST) MIME-Version: 1.0 References: <000901da3603$10e97cb0$32bc7610$@nextmovesoftware.com> <7518ec8d-ac4a-4d3e-a063-caa0ee520acf@gmail.com> <000f01da3646$57092a40$051b7ec0$@nextmovesoftware.com> In-Reply-To: From: Andrew Pinski Date: Sun, 24 Dec 2023 01:28:54 -0800 Message-ID: Subject: Re: [PATCH v3] EXPR: Emit an truncate if 31+ bits polluted for SImode To: YunQiang Su Cc: Roger Sayle , Jeff Law , GCC Patches Content-Type: multipart/alternative; boundary="000000000000b49228060d3e143f" X-Spam-Status: No, score=-0.6 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000b49228060d3e143f Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sun, Dec 24, 2023, 01:18 YunQiang Su wrote: > Roger Sayle =E4=BA=8E2023=E5=B9=B412=E6=9C= =8824=E6=97=A5=E5=91=A8=E6=97=A5 16:51=E5=86=99=E9=81=93=EF=BC=9A > > > > > > > What's exceedingly weird is T_N_T_M_P (DImode, SImode) isn't actually= a > > > truncation! The output precision is first, the input precision is > second. The docs > > > explicitly state the output precision should be smaller than the input > precision > > > (which makes sense for truncation). > > > > > > That's where I'd start with trying to untangle this mess. > > > > Thanks (both) for correcting my misunderstanding. > > At the very least might I suggest that we introduce a new > > TRULY_NOOP_EXTENSION_MODES_P target hook that MIPS > > can use for this purpose? It'd help reduce confusion, and keep > > the documentation/function naming correct. > > > > Yes. It is good for me. > T_N_T_M_P is a really confusion naming. > > > When Richard Sandiford "hookized" truly_noop_truncation in 2017 > > https://gcc.gnu.org/legacy-ml/gcc-patches/2017-09/msg00836.html > > he mentions the inprec/outprec confusion [deciding not to add a > > gcc_assert outprec < inprec here, which might be a good idea]. > > > > The next question is whether this is just > > TRULY_NOOP_SIGN_EXTENSION_MODES_P > > or whether there are any targets that usefully ensure some modes > > are zero-extended forms of others. TRULY_NOOP_ZERO_EXTENSION... > > > > I guess ARM64 is the one TRULY_NOOP_ZERO_EXTENSION? > I am not 100% convinced here that is true. Yes aarch64 has many zero-extend instruction and ones that ignore the top 32 bits. That is a different requirement from mips. > > My vote is that a DINS instruction that updates the most significant > > bit of an SImode value should then expand or define_insn_and_split > > with an explicit following sign-extension operation. To avoid this bei= ng > > eliminated by the RTL optimizers/combine the DINS should return a > > DImode result, with the following extension truncating it to canonical > > Is it this one? > https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626137.html > > > SImode form. This preserves the required backend invariant (and > > doesn't require tweaking machine-independent code in combine). > > SImode DINS instructions that don't/can't affect the MSB, can be a > > single SImode instruction. > > > > Yes. As most of MIPS microarchitecture, INS may have slight better > performance than DINS. > This is not true. Cavium's octeon had the same performance characteristics for dins and ins. Though I doubt that microarch matters any more. Thanks, Andrew > While, I am worrying that: will some body do something like > INS ,,24,8 > In this case, if is not sign-extended, the result will be > UNPREDICTABLE. > For this, now, I prefer to use DINS and append a SLL. > > I tried to write a C code that can produce this case, but not yet > success. > > > > Cheers, > > Roger > > -- > > > > > --000000000000b49228060d3e143f--