From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 113898 invoked by alias); 3 Feb 2020 17:47:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 113889 invoked by uid 89); 3 Feb 2020 17:47:40 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-14.8 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LOTSOFHASH,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=HX-Languages-Length:4622, H*F:U*pinskia, CUT X-HELO: mail-vs1-f46.google.com Received: from mail-vs1-f46.google.com (HELO mail-vs1-f46.google.com) (209.85.217.46) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Feb 2020 17:47:38 +0000 Received: by mail-vs1-f46.google.com with SMTP id x123so9518628vsc.2 for ; Mon, 03 Feb 2020 09:47:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=wsXI/eWHWf36IXIiGmPmWH/v9z3ViAtekr3hRIqq4jw=; b=fbxAoqrwUFh+wYp0/Ud8lHH0AuNcXDJEbQc3ePEZTHZO9Fyad/81xiZ+j6IyGieLEX Sgc1pZXJZOyLsQy5vlUKDc44oA9Qf8q1BOaRo8wWnJ0o2+QLqryieVfT5Tz80fusJgiX tfUxAG88XuDPpBEIivJzyECn1kTcffbpHDYzWW97XTqdRx0FtgQSXoIYtjmBUJl91gwn fedvEutHwySxa1bUuZ6OuqgaiprPulNEEpuLZyRYO95ol94pwRv5mdh9NaplmG7umCr7 MmaIJl2JSVgklfBbpzwoZ/ZN05vNxJNX3PcF665ChsFBtRbI2Yp+EtmRJi1tdCoSak/B gs9A== MIME-Version: 1.0 References: In-Reply-To: From: Andrew Pinski Date: Mon, 03 Feb 2020 17:47:00 -0000 Message-ID: Subject: Re: [PATCH][AArch64] Improve popcount expansion To: Wilco Dijkstra Cc: GCC Patches , Kyrylo Tkachov , Richard Sandiford , Richard Earnshaw Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2020-02/txt/msg00099.txt.bz2 On Mon, Feb 3, 2020 at 7:02 AM Wilco Dijkstra wrote: > > The popcount expansion uses umov to extend the result and move it back > to the integer register file. If we model ADDV as a zero-extending > operation, fmov can be used to move back to the integer side. This > results in a ~0.5% speedup on deepsjeng on Cortex-A57. > > A typical __builtin_popcount expansion is now: > > fmov s0, w0 > cnt v0.8b, v0.8b > addv b0, v0.8b > fmov w0, s0 > > Bootstrap OK, passes regress. You might want to add a testcase that the autovectorizers too. Something like this: unsigned f(unsigned char *a) { unsigned char b = 0; for(int i = 0; i < 16; i++) b+=a[i]; return b; } --- CUT --- Currently we get also: ldr q0, [x0] addv b0, v0.16b umov w0, v0.b[0] ret Otherwise LGTM. Thanks, Andrew > > ChangeLog > 2020-02-02 Wilco Dijkstra > > gcc/ > * config/aarch64/aarch64.md (popcount2): Improve expansion. > * config/aarch64/aarch64-simd.md > (aarch64_zero_extend_reduc_plus_): New pattern. > * config/aarch64/iterators.md (VDQV_E): New iterator. > testsuite/ > * gcc.target/aarch64/popcnt2.c: New test. > > -- > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > index 97f46f96968a6bc2f93bbc812931537b819b3b19..34765ff43c1a090a31e2aed64ce95510317ab8c3 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -2460,6 +2460,17 @@ (define_insn "aarch64_reduc_plus_internal" > [(set_attr "type" "neon_reduc_add")] > ) > > +;; ADDV with result zero-extended to SI/DImode (for popcount). > +(define_insn "aarch64_zero_extend_reduc_plus_" > + [(set (match_operand:GPI 0 "register_operand" "=w") > + (zero_extend:GPI > + (unspec: [(match_operand:VDQV_E 1 "register_operand" "w")] > + UNSPEC_ADDV)))] > + "TARGET_SIMD" > + "add\\t%0, %1." > + [(set_attr "type" "neon_reduc_add")] > +) > + > (define_insn "aarch64_reduc_plus_internalv2si" > [(set (match_operand:V2SI 0 "register_operand" "=w") > (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")] > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 86c2cdfc7973f4b964ba233cfbbe369b24e0ac10..5edc76ee14b55b2b4323530e10bd22b3ffca483e 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -4829,7 +4829,6 @@ (define_expand "popcount2" > { > rtx v = gen_reg_rtx (V8QImode); > rtx v1 = gen_reg_rtx (V8QImode); > - rtx r = gen_reg_rtx (QImode); > rtx in = operands[1]; > rtx out = operands[0]; > if(mode == SImode) > @@ -4843,8 +4842,7 @@ (define_expand "popcount2" > } > emit_move_insn (v, gen_lowpart (V8QImode, in)); > emit_insn (gen_popcountv8qi2 (v1, v)); > - emit_insn (gen_reduc_plus_scal_v8qi (r, v1)); > - emit_insn (gen_zero_extendqi2 (out, r)); > + emit_insn (gen_aarch64_zero_extend_reduc_plus_v8qi (out, v1)); > DONE; > }) > > diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md > index fc973086cb91ae0dc54eeeb0b832d522539d7982..926779bf2442fa60d184ef17308f91996d6e8d1b 100644 > --- a/gcc/config/aarch64/iterators.md > +++ b/gcc/config/aarch64/iterators.md > @@ -208,6 +208,9 @@ (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI]) > ;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes. > (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI]) > > +;; Advanced SIMD modes for Integer reduction across lanes (zero/sign extended). > +(define_mode_iterator VDQV_E [V8QI V16QI V4HI V8HI]) > + > ;; All double integer narrow-able modes. > (define_mode_iterator VDN [V4HI V2SI DI]) > > diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt2.c b/gcc/testsuite/gcc.target/aarch64/popcnt2.c > new file mode 100644 > index 0000000000000000000000000000000000000000..e321858afa4d6ecb6fc7348f39f6e5c6c0c46147 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/popcnt2.c > @@ -0,0 +1,21 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2" } */ > + > +unsigned > +foo (int x) > +{ > + return __builtin_popcount (x); > +} > + > +unsigned long > +foo1 (int x) > +{ > + return __builtin_popcount (x); > +} > + > +/* { dg-final { scan-assembler-not {popcount} } } */ > +/* { dg-final { scan-assembler-times {cnt\t} 2 } } */ > +/* { dg-final { scan-assembler-times {fmov} 4 } } */ > +/* { dg-final { scan-assembler-not {umov} } } */ > +/* { dg-final { scan-assembler-not {uxtw} } } */ > +/* { dg-final { scan-assembler-not {sxtw} } } */ >