From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23909 invoked by alias); 25 Jun 2017 21:38:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 23896 invoked by uid 89); 25 Jun 2017 21:38:26 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=peoples, exhaustive, people's, meet X-HELO: mail-yb0-f173.google.com Received: from mail-yb0-f173.google.com (HELO mail-yb0-f173.google.com) (209.85.213.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 25 Jun 2017 21:38:24 +0000 Received: by mail-yb0-f173.google.com with SMTP id b81so5369861yba.2 for ; Sun, 25 Jun 2017 14:38:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=ZG64gGARB385ZW4aS6D+ErwBxGpYoYiMQiKu+CkIX9o=; b=AD7oSavLUHKWfJaiJfn+YTwN7L2eVrQ64od0Ys82pan/LsXSh651/Nh5nlfY6DHnAr T3RNTXqHg90iKsvLviJBH7RwzG6AYABhmJAWIRW4jCGYZQDEpeQkLJYdYqPHiqdPcVH7 W2PyZXMNiK1BnrKmXbVgIvrAo3izETrE7yLstG76E8erBTRxKWrJTJ741J3uZFXCqQKJ IFzJqcW9lHb6hQmo4CQAe8aa474fBpQ/xS7WM01fW5gN7/DGEHHeLz79NT5g3uP6YTbW xTDnYeJgaFYELEhlcq/5ZPW55DsPtePpWoRnqwsJQ7IbNfN1tEJpE4/eHrQLc6FWsLt0 uhgg== X-Gm-Message-State: AKS2vOwrtMmYNKRjKckxeMksn9+M7fBH5ELc4uQUHGAYKWi7ablnJOKv nUdpvk1AjaKUtWj+Fc4SMV0ojTAepg== X-Received: by 10.37.176.140 with SMTP id f12mr13016855ybj.231.1498426702948; Sun, 25 Jun 2017 14:38:22 -0700 (PDT) MIME-Version: 1.0 Received: by 10.129.47.200 with HTTP; Sun, 25 Jun 2017 14:38:22 -0700 (PDT) In-Reply-To: <59368A74.2060908@foss.arm.com> References: <59368A74.2060908@foss.arm.com> From: Andrew Pinski Date: Sun, 25 Jun 2017 21:38:00 -0000 Message-ID: Subject: Re: [RFC][AARCH64]Add 'r' integer register operand modifier. Document the common asm modifier for aarch64 target. To: Renlin Li Cc: "gcc-patches@gcc.gnu.org" , James Greenhalgh , Ramana Radhakrishnan , Richard Earnshaw Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2017-06/txt/msg01874.txt.bz2 On Tue, Jun 6, 2017 at 3:56 AM, Renlin Li wrote: > Hi all, > > In this patch, a new integer register operand modifier 'r' is added. This > will use the > proper register name according to the mode of corresponding operand. > > 'w' register for scalar integer mode smaller than DImode > 'x' register for DImode > > This allows more flexibility and would meet people's expectations. > It will help for ILP32 and LP64, and big-endian case. > > A new section is added to document the AArch64 operand modifiers which might > be used in inline assembly. It's not an exhaustive list covers every > modifier. > Only the most common and useful ones are documented. > > The default behavior of integer operand without modifier is clearly > documented > as well. It's not changed so that the patch shouldn't break anything. > > So with this patch, it should resolve the issues in PR63359. > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63359 > > > aarch64-none-elf regression test Okay. Okay to check in? I think 'r' modifier is very fragile and can be used incorrectly and wrong in some cases really.. I like the documentation though. Thanks, Andrew > > gcc/ChangeLog: > > 2017-06-06 Renlin Li > > PR target/63359 > * config/aarch64/aarch64.c (aarch64_print_operand): Add 'r' > modifier. > * doc/extend.texi (AArch64Operandmodifiers): New section.