From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 94456 invoked by alias); 21 Mar 2017 05:37:26 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 94367 invoked by uid 89); 21 Mar 2017 05:37:16 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.4 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=no version=3.3.2 spammy= X-HELO: mail-yw0-f180.google.com Received: from mail-yw0-f180.google.com (HELO mail-yw0-f180.google.com) (209.85.161.180) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 Mar 2017 05:37:14 +0000 Received: by mail-yw0-f180.google.com with SMTP id v198so103526347ywc.2 for ; Mon, 20 Mar 2017 22:37:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=Rsmh1Q9Wysxvqrceovxnzk/YbNDAPhSMM02VjoMfKtE=; b=XY9UnOlvhZs7pKlBjP/vTXgPpfoZs05qhtMezbj2w6dqKQCog7Qf2/td75DhLcK0r/ c0+1nPOmTf2xt8oHOUi/lU1f8a5X5S+7z6jU0+WPoLoR/SoyLT78corQkIberkvO8vR1 MA8XwP90YS49fXHoB+SbYBTPbYp6S3eTuTv7m47f8DIxdWVfAFHIlowzpSIwVohKCTys +8y5XEWkk4rgldjDQFcQ40x025ueoMSlp9IIUTZ3T3dcMq8ZcamcFOwyEAiv+NrGIiFG Wi3nD/vxDy+vyzhhI6RVZ1+JAZ7c5JMRBuuCkGT8B0kJb4Gm0W+L6ZgaqYFYHVnXP8m6 ZNKg== X-Gm-Message-State: AFeK/H22MgsfliWfz4tm+07oE0THxSBWiovawMKDrFaS55cTaFTn2RneGN9lSIyEA8A6nHvKK4SjXYfhQ9hGJg== X-Received: by 10.129.78.5 with SMTP id c5mr3053152ywb.85.1490074634308; Mon, 20 Mar 2017 22:37:14 -0700 (PDT) MIME-Version: 1.0 Received: by 10.129.174.101 with HTTP; Mon, 20 Mar 2017 22:37:13 -0700 (PDT) In-Reply-To: References: From: Andrew Pinski Date: Tue, 21 Mar 2017 05:37:00 -0000 Message-ID: Subject: Re: [PATCH][AArch64] Implement ALU_BRANCH fusion To: Wilco Dijkstra Cc: "Naveen.Hurugalawadi@cavium.com" , "Andrew.pinski@cavium.com" , Kyrylo Tkachov , James Greenhalgh , nd , GCC Patches Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2017-03/txt/msg01077.txt.bz2 On Wed, Mar 15, 2017 at 8:20 AM, Wilco Dijkstra wrote: > Hi, > > I think the patch isn't quite complete yet. You will also need changes in > generic code. Currently sched_macro_fuse_insns() does: > > if (any_condjump_p (insn)) > { > unsigned int condreg1, condreg2; > rtx cc_reg_1; > targetm.fixed_condition_code_regs (&condreg1, &condreg2); > cc_reg_1 = gen_rtx_REG (CCmode, condreg1); > prev = prev_nonnote_nondebug_insn (insn); > if (!reg_referenced_p (cc_reg_1, PATTERN (insn)) > || !prev > || !modified_in_p (cc_reg_1, prev)) > return; > } > > Ie. it explicitly looks for a flag-setting ALU instruction whose condition is > used by a conditional branch, so none of the cases in your patch can match. > > Note this code also excludes all CBZ type branches as fusion candidates, > is that intended too? It is not intended that way; I did not even notice it after the previous changes to make the macro_fusion more generic. I wonder how this code ever worked for the folks before we started to touch it :). Naveen, Basically the idea is to push the check for CC usage into the target macros (macro_fusion_pair_p in i386.c and aarch64.c are the only usage of compare/branch fusion) instead of keeping it in the general code. Also in aarch64.c's macro fusion you need check that the branch instruction uses the same register as the other instruction sets like the other code in this area. Thanks, Andrew Pinski > > Wilco