Re: [PATCH/AARCH64] Decimal floating point support for AARCH64

[Andrew Pinski <apinski@cavium.com>]

On Fri, Jul 21, 2017 at 2:45 PM, Peter Bergner <bergner@vnet.ibm.com> wrote:
> On 7/13/17 7:12 PM, Andrew Pinski wrote:
>>   This patch adds Decimal floating point support to aarch64.  It is
>> the base support in that since there is no hardware support for DFP,
>> it just defines the ABI.  The ABI I chose is that _Decimal32 is
>> treated like float, _Decimal64 is treated like double and _Decimal128
>> is treated like long double.  In that they are passed via the floating
>> registers (sN, dN, qN).
>> Is this ok an ABI?
>
> It depends on whether AARCH ever plans on implementing HW DFP.
> On POWER, we handle things similarly to what you mention above,
> except for one extra constraint for _Decimal128 and that is that
> they must live in even/odd register pairs.  This was due to how
> the instructions were implemented in the HW, they required even/odd
> reg pairs.
>
> If there's zero chance AARCH ever implements HW DFP, then you're
> probably fine with the above, but if you go with the above and HW DFP
> is eventually added, then the HW would need handle even/odd and
> odd/even register pairs in it's instructions...or you'd need to
> add potential prologue/epilogue code to move formal args into
> even/odd regs if the HW demands it.  If there is a non-zero chance
> or you just want to be safe, you could enforce even/odd reg usage
> in the ABI upfront.

So right now how TFmode is handled on AARCH64 not as a pair of 64bit
registers but rather one 128bit registers (qN registrer; the floating
point register and the SIMD register set on AARCH64 overlap already).
So handling TDmode like TFmode is more natural for AARCH64 than most
arch.  that the DFP hw support for _Decimal128 on AARCH64 would take
the values in the qN register rather than a pair of registers.

Thanks,
Andrew Pinski

>
> Peter
>