From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id 84DEC3854578 for ; Thu, 17 Nov 2022 18:25:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 84DEC3854578 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pl1-x631.google.com with SMTP id io19so2393784plb.8 for ; Thu, 17 Nov 2022 10:25:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=mxgJpM4vinx4h/0MSCVXYjRPsKmZdIJt746jo/dtvd4=; b=KBvki7/TSRkGE9t3VzLDYQclRZACewG1UEvyEE5qR+u56K84N5eybUfdsdIuGJ5vkB Gdl9QOYM0htVsJ2LmRVGFNmUT8zTwfi4gJ7PUBlS+5u9rl0ahNkVsjrV6V+DOOuGv99U JVKa004dTyu2YvkGzVO3uYOCfdAE2tUAlinUfkW9oAdzxSSunJ306DM0AZs/9dekhRXA YY1tKyUDFuyTKjEtwLtz2j7sT3LhMuhyBryrtZiikyo5Ip6lMWQJc8GkvQji14MG0arl l8TYM91/9Y4pLSZpl0Bf3GhgtSgISzMG4cqRgOo3ls5tvs87bkUZ9KFtJEJ3ldfh1jx/ YzxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=mxgJpM4vinx4h/0MSCVXYjRPsKmZdIJt746jo/dtvd4=; b=es5hEGJLUbqWh2nOT6n4F2VKLVOI96bY4070QGluBAf0LAEFVRr+Zt6QpFvFybo9Zx wzJB+9I3aoeoI2d2mD0AZWy8EDaP7dN+A3+KTexXzwguXw7ifBy/Eb0tBkiFnH9UDyFJ qQS9mIZoMx0g20480D+8f4ej3OQ7GKf8zs8tFI6rCUTCwGJ1nQHqVNo6Du6TsB1Td0xf lEAENKWguaEiLIonoZ2H6chqIFBN4WCDf81Os+HbO3RYJF8JfeAeu4q55rAlOX79iR3L kpk+INC9ezRJTSaLTQS/1/0y0OHnVzjCP9vWGy+8ENTKcURLa4WPDOxsTHspVieshbK8 D26Q== X-Gm-Message-State: ANoB5pnxxvROF0CElSavGpmawddAhA+DW/0mwGQyy6jzQyALgq6YaDm3 AfYqMEIgQdcDnBpRW1fuerQ1e1kVMWqxnhyy/7k= X-Google-Smtp-Source: AA0mqf5SAqU/fDLawNJpCzMEGVuoM6c3gyhadysGxkW1LU1aDBffgsO182vwX/GpMOleNwE5uwAEaM9TvAzs03nWtZY= X-Received: by 2002:a17:90a:ac07:b0:206:238e:1379 with SMTP id o7-20020a17090aac0700b00206238e1379mr3906121pjq.180.1668709553385; Thu, 17 Nov 2022 10:25:53 -0800 (PST) MIME-Version: 1.0 References: <20221113204858.4062163-1-philipp.tomsich@vrull.eu> In-Reply-To: <20221113204858.4062163-1-philipp.tomsich@vrull.eu> From: Andrew Pinski Date: Thu, 17 Nov 2022 10:25:40 -0800 Message-ID: Subject: Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs To: Philipp Tomsich Cc: gcc-patches@gcc.gnu.org, Christoph Muellner , Kito Cheng , Vineet Gupta , Jeff Law , Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sun, Nov 13, 2022 at 12:51 PM Philipp Tomsich wrote: > > Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) ..." > that can be expressed as bexti + bexti + andn. Can't you also handle if ((a & twobits) == 0) case doing a similar thing. That is: two bexti + and and then compare against zero which is exactly the same # of instructions as the above case. > > gcc/ChangeLog: > > * config/riscv/bitmanip.md (*branch_mask_twobits_equals_singlebit): > Handle "if ((a & T) == C)" using Zbs, when T has 2 bits set and C has one > of these tow bits set. > * config/riscv/predicates.md (const_twobits_operand): New predicate. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/zbs-if_then_else-01.c: New test. > > Signed-off-by: Philipp Tomsich > --- > > gcc/config/riscv/bitmanip.md | 42 +++++++++++++++++++ > gcc/config/riscv/predicates.md | 5 +++ > .../gcc.target/riscv/zbs-if_then_else-01.c | 20 +++++++++ > 3 files changed, 67 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c > > diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md > index 7a8f4e35880..2cea394671f 100644 > --- a/gcc/config/riscv/bitmanip.md > +++ b/gcc/config/riscv/bitmanip.md > @@ -690,3 +690,45 @@ > "TARGET_ZBS" > [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) > (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))]) > + > +;; IF_THEN_ELSE: test for 2 bits of opposite polarity > +(define_insn_and_split "*branch_mask_twobits_equals_singlebit" > + [(set (pc) > + (if_then_else (match_operator 1 "equality_operator" > + [(and:X (match_operand:X 2 "register_operand" "r") > + (match_operand:X 3 "const_twobits_operand" "i")) > + (match_operand:X 4 "single_bit_mask_operand" "i")]) > + (label_ref (match_operand 0 "" "")) > + (pc))) > + (clobber (match_scratch:X 5 "=&r")) > + (clobber (match_scratch:X 6 "=&r"))] > + "TARGET_ZBS && TARGET_ZBB && !SMALL_OPERAND (INTVAL (operands[3]))" > + "#" > + "&& reload_completed" > + [(set (match_dup 5) (zero_extract:X (match_dup 2) > + (const_int 1) > + (match_dup 8))) > + (set (match_dup 6) (zero_extract:X (match_dup 2) > + (const_int 1) > + (match_dup 9))) > + (set (match_dup 6) (and:X (not:X (match_dup 6)) (match_dup 5))) > + (set (pc) (if_then_else (match_op_dup 1 [(match_dup 6) (const_int 0)]) > + (label_ref (match_dup 0)) > + (pc)))] > +{ > + unsigned HOST_WIDE_INT twobits_mask = UINTVAL (operands[3]); > + unsigned HOST_WIDE_INT singlebit_mask = UINTVAL (operands[4]); > + > + /* Make sure that the reference value has one of the bits of the mask set */ > + if ((twobits_mask & singlebit_mask) == 0) > + FAIL; > + > + int setbit = ctz_hwi (singlebit_mask); > + int clearbit = ctz_hwi (twobits_mask & ~singlebit_mask); > + > + operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == NE ? EQ : NE, > + mode, operands[6], GEN_INT(0)); > + > + operands[8] = GEN_INT (setbit); > + operands[9] = GEN_INT (clearbit); > +}) > diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md > index 490bff688a7..6e34829a59b 100644 > --- a/gcc/config/riscv/predicates.md > +++ b/gcc/config/riscv/predicates.md > @@ -321,6 +321,11 @@ > (and (match_code "const_int") > (match_test "popcount_hwi (~UINTVAL (op)) == 2"))) > > +;; A CONST_INT operand that has exactly two bits set. > +(define_predicate "const_twobits_operand" > + (and (match_code "const_int") > + (match_test "popcount_hwi (UINTVAL (op)) == 2"))) > + > ;; A CONST_INT operand that fits into the unsigned half of a > ;; signed-immediate after the top bit has been cleared. > (define_predicate "uimm_extra_bit_operand" > diff --git a/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c b/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c > new file mode 100644 > index 00000000000..d249a841ff9 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gc_zbb_zbs -mabi=lp64" } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ It would be useful to add a rv32 testcase too. Thanks, Andrew Pinski > + > +void g(); > + > +void f1 (long a) > +{ > + if ((a & ((1ul << 33) | (1 << 4))) == (1ul << 33)) > + g(); > +} > + > +void f2 (long a) > +{ > + if ((a & 0x12) == 0x10) > + g(); > +} > + > +/* { dg-final { scan-assembler-times "bexti\t" 2 } } */ > +/* { dg-final { scan-assembler-times "andn\t" 1 } } */ > -- > 2.34.1 >