From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by sourceware.org (Postfix) with ESMTPS id E1CC23858D33 for ; Tue, 21 Nov 2023 23:05:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E1CC23858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E1CC23858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::434 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700607936; cv=none; b=YSOIUW6kYeAG2AFZLeD27xvJ+4gbHq96yoDmPW2gzwt9MSFdEbgIp4uJnnIUz1iuoEcbREBChXZYHQrA4pZCw2Lkn+B06tqBBE/6g7quKUq82SS3oVO0kk3HI74rIssl9EAO+XFdmSGjwMMzGOw8uPGshZWcvwDZRh19eBXr4XM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700607936; c=relaxed/simple; bh=YCvzgDPpP8M0a85JBS3kFlWa97VlLYEH0ylj0D/veHQ=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=JjWNA5K9ZaM9Lz5LSKkNNwBv3Jn63OzeAls6LvU+SiUmMMjyt6Bz++FhuH8BAQCAvdk2CvArEeJMTu0/N73/ohsrofNLIl4V35UjXN5Pt9su6UIp/BDpyWcpnDGJhbbZUXyZUpXazbo7lT6MTtfknP0DujwBpHHxDWxhS7q/ugw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-6c33ab26dddso5366039b3a.0 for ; Tue, 21 Nov 2023 15:05:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700607932; x=1701212732; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=NvUwZxJ8/jhYGv8fJ9dS682r/eJBUZ2Apw9noNWWNWI=; b=CDE3glBMtNtCrukaU5d/duvGfxV8RRLc+1OdTtwq7UyU7sa7LAgzafCTfvIUVP8Tgh 6oVXxEplkVG3VEgpUn58F48Gz2deeK8qOb8RoCrVfqEotxh3oqo58QC0OI3nG0ATNUiY 78xo9FTV/W+pfkUkLbWeOmENKZIZQhOfDh8z7vLaP50mS1pu+91EgsoZRXLdjW3axH19 l84RKRtH5hHcpKaN9o26bDViLj5RrdxVvpwp1qjTjAw+XT3h9bM93rRbu7CE4j73mmF4 ePn8QuVPU7i/JRff6K2NEX8dcsGwTbMrNwFmWgVGbOPvz29FnBOtsjd4pRJ16Pqo6y4p RrrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700607932; x=1701212732; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NvUwZxJ8/jhYGv8fJ9dS682r/eJBUZ2Apw9noNWWNWI=; b=CAD6g4sF5hysdtjE34A4JiQAiznmvzO+n5YM8DzC8fLj/+AXaBY2+b9wKKTk5G94tA TgnHOcIjcThuUqAnlR52xdREUAE6yPHVIhAiTjLgZ1GBv0lnz4LBHbPE9BnMJiSNC020 BTN+Fyx64YyGnaWk/iKZ7+iTLXeWR5YEbEnWu9WDulfUS5G5rA+G+zV0NJlKBFueAoie 65QSxMEZktuMaKEJBdfwWxXMLpJHZRtuiADmPEn0i4YQtXvY9J9cPcV61CgA+diPIY7o +De9iGSzZoDOAZdfQbhgoCiSN/DVCcPBwSINRgNLrYoHeNdJplnVvy1L+b5SmyHOs0eG FsMQ== X-Gm-Message-State: AOJu0YxCIYi7ZKpCMTzSBvwntVWm/Ymp83f7hQZqV3outDPyWZvKZIL5 HzpKo8b1BM3LTTjOGUmYrbGFRHDHbt3D0MHeB0i/vTjfkJKCwA== X-Google-Smtp-Source: AGHT+IFwxkyoA7mpC8ckgM/NtNN7dAc4eidKGksJU54MAPJsAQxdRUrFia65ufdIO5/ponKRDcxKVHM3OqJTAytiACs= X-Received: by 2002:a05:6a20:3d85:b0:18a:e99d:cf4e with SMTP id s5-20020a056a203d8500b0018ae99dcf4emr578448pzi.22.1700607931454; Tue, 21 Nov 2023 15:05:31 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Andrew Pinski Date: Tue, 21 Nov 2023 15:05:19 -0800 Message-ID: Subject: Re: [PATCH]AArch64 Add pattern for unsigned widenings (uxtl) to zip{1,2} To: Tamar Christina Cc: gcc-patches@gcc.gnu.org, nd@arm.com, Richard.Earnshaw@arm.com, Marcus.Shawcroft@arm.com, Kyrylo.Tkachov@arm.com, richard.sandiford@arm.com, "Andrew Pinski (QUIC)" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_LOTSOFHASH,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Nov 21, 2023 at 2:43=E2=80=AFPM Andrew Pinski w= rote: > > On Wed, Nov 15, 2023 at 6:42=E2=80=AFAM Tamar Christina wrote: > > > > Hi All, > > > > This changes unpack instructions to use zip{1,2} when doing a zero-exte= nding > > widening operation. Permutes generally have a higher throughput than t= he > > widening operations. Zeros are shuffled into the top half of the regist= ers. > > > > The testcase > > > > void d2 (unsigned * restrict a, unsigned short *b, int n) > > { > > for (int i =3D 0; i < (n & -8); i++) > > a[i] =3D b[i]; > > } > > > > now generates: > > > > movi v1.4s, 0 > > .L3: > > ldr q0, [x1], 16 > > zip1 v2.8h, v0.8h, v1.8h > > zip2 v0.8h, v0.8h, v1.8h > > stp q2, q0, [x0] > > add x0, x0, 32 > > cmp x1, x2 > > bne .L3 > > > > > > instead of: > > > > .L3: > > ldr q0, [x1], 16 > > uxtl v1.4s, v0.4h > > uxtl2 v0.4s, v0.8h > > stp q1, q0, [x0] > > add x0, x0, 32 > > cmp x1, x2 > > bne .L3 > > > > Since we need the extra 0 register we do this only for the vectorizer's= lo/hi > > pairs when we know the 0 will be floated outside of the loop. > > > > This gives an 8% speed-up in Imagick in SPECCPU 2017 on Neoverse V2. > > > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > > > Ok for master? > > > > Thanks, > > Tamar > > > > gcc/ChangeLog: > > > > * config/aarch64/aarch64-simd.md (vec_unpack_lo_ > vec_unpack_lo_ > (vec_unpacku_lo_ > vec_unpacku_lo_ > (aarch64_usubw__zip): New. > > (aarch64_uaddw__zip): New. > > * config/aarch64/iterators.md (PERM_EXTEND, perm_index): New. > > (perm_hilo): Add UNSPEC_ZIP1, UNSPEC_ZIP2. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/aarch64/simd/vmovl_high_1.c: Update codegen. > > * gcc.target/aarch64/uxtl-combine-1.c: New test. > > * gcc.target/aarch64/uxtl-combine-2.c: New test. > > * gcc.target/aarch64/uxtl-combine-3.c: New test. > > * gcc.target/aarch64/uxtl-combine-4.c: New test. > > * gcc.target/aarch64/uxtl-combine-5.c: New test. > > * gcc.target/aarch64/uxtl-combine-6.c: New test. > > You have a few typos in the testcases which causes: > ERROR: gcc.target/aarch64/uxtl-combine-4.c: error executing dg-final: > invalid command name "scan-assembler-time" > ERROR: gcc.target/aarch64/uxtl-combine-5.c: error executing dg-final: > invalid command name "scan-assembler-time" > ERROR: gcc.target/aarch64/uxtl-combine-6.c: error executing dg-final: > invalid command name "scan-assembler-time" You must not have done some good testing since it also caused the following= : FAIL: gcc.dg/vect/slp-widen-mult-half.c (test for excess errors) FAIL: gcc.dg/vect/slp-widen-mult-half.c -flto -ffat-lto-objects (test for excess errors) UNRESOLVED: gcc.dg/vect/slp-widen-mult-half.c -flto -ffat-lto-objects compilation failed to produce executable UNRESOLVED: gcc.dg/vect/slp-widen-mult-half.c compilation failed to produce executable FAIL: gcc.dg/vect/vect-avg-9.c (test for excess errors) FAIL: gcc.dg/vect/vect-avg-9.c -flto -ffat-lto-objects (test for excess err= ors) UNRESOLVED: gcc.dg/vect/vect-avg-9.c -flto -ffat-lto-objects compilation failed to produce executable UNRESOLVED: gcc.dg/vect/vect-avg-9.c compilation failed to produce executab= le FAIL: gcc.dg/vect/vect-outer-4f.c (test for excess errors) FAIL: gcc.dg/vect/vect-outer-4f.c -flto -ffat-lto-objects (test for excess errors) UNRESOLVED: gcc.dg/vect/vect-outer-4f.c -flto -ffat-lto-objects compilation failed to produce executable UNRESOLVED: gcc.dg/vect/vect-outer-4f.c compilation failed to produce execu= table FAIL: gcc.dg/vect/vect-outer-4g.c (test for excess errors) FAIL: gcc.dg/vect/vect-outer-4g.c -flto -ffat-lto-objects (test for excess errors) UNRESOLVED: gcc.dg/vect/vect-outer-4g.c -flto -ffat-lto-objects compilation failed to produce executable UNRESOLVED: gcc.dg/vect/vect-outer-4g.c compilation failed to produce execu= table FAIL: gcc.dg/vect/vect-outer-4i.c (test for excess errors) FAIL: gcc.dg/vect/vect-outer-4i.c -flto -ffat-lto-objects (test for excess errors) UNRESOLVED: gcc.dg/vect/vect-outer-4i.c -flto -ffat-lto-objects compilation failed to produce executable UNRESOLVED: gcc.dg/vect/vect-outer-4i.c compilation failed to produce execu= table FAIL: gcc.dg/vect/vect-outer-4k.c (test for excess errors) FAIL: gcc.dg/vect/vect-outer-4k.c -flto -ffat-lto-objects (test for excess errors) UNRESOLVED: gcc.dg/vect/vect-outer-4k.c -flto -ffat-lto-objects compilation failed to produce executable UNRESOLVED: gcc.dg/vect/vect-outer-4k.c compilation failed to produce execu= table FAIL: gcc.dg/vect/vect-outer-4l.c (test for excess errors) FAIL: gcc.dg/vect/vect-outer-4l.c -flto -ffat-lto-objects (test for excess errors) UNRESOLVED: gcc.dg/vect/vect-outer-4l.c -flto -ffat-lto-objects compilation failed to produce executable UNRESOLVED: gcc.dg/vect/vect-outer-4l.c compilation failed to produce execu= table FAIL: gcc.dg/vect/vect-outer-4m-big-array.c (test for excess errors) FAIL: gcc.dg/vect/vect-outer-4m-big-array.c -flto -ffat-lto-objects (test for excess errors) UNRESOLVED: gcc.dg/vect/vect-outer-4m-big-array.c -flto -ffat-lto-objects compilation failed to produce executable UNRESOLVED: gcc.dg/vect/vect-outer-4m-big-array.c compilation failed to produce executable FAIL: gcc.dg/vect/vect-outer-4m.c (test for excess errors) FAIL: gcc.dg/vect/vect-outer-4m.c -flto -ffat-lto-objects (test for excess errors) UNRESOLVED: gcc.dg/vect/vect-outer-4m.c -flto -ffat-lto-objects compilation failed to produce executable UNRESOLVED: gcc.dg/vect/vect-outer-4m.c compilation failed to produce execu= table FAIL: gcc.dg/vect/vect-over-widen-10.c (test for excess errors) FAIL: gcc.dg/vect/vect-over-widen-10.c -flto -ffat-lto-objects (test for excess errors) UNRESOLVED: gcc.dg/vect/vect-over-widen-10.c -flto -ffat-lto-objects compilation failed to produce executable UNRESOLVED: gcc.dg/vect/vect-over-widen-10.c compilation failed to produce executable FAIL: gcc.dg/vect/vect-over-widen-12.c (test for excess errors) FAIL: gcc.dg/vect/vect-over-widen-12.c -flto -ffat-lto-objects (test for excess errors) UNRESOLVED: gcc.dg/vect/vect-over-widen-12.c -flto -ffat-lto-objects compilation failed to produce executable UNRESOLVED: gcc.dg/vect/vect-over-widen-12.c compilation failed to produce executable FAIL: gcc.dg/vect/vect-pr111779.c (test for excess errors) FAIL: gcc.dg/vect/vect-pr111779.c -flto -ffat-lto-objects (test for excess errors) UNRESOLVED: gcc.dg/vect/vect-pr111779.c -flto -ffat-lto-objects compilation failed to produce executable UNRESOLVED: gcc.dg/vect/vect-pr111779.c compilation failed to produce execu= table FAIL: gcc.dg/vect/vect-widen-mult-half.c (test for excess errors) FAIL: gcc.dg/vect/vect-widen-mult-half.c -flto -ffat-lto-objects (test for excess errors) UNRESOLVED: gcc.dg/vect/vect-widen-mult-half.c -flto -ffat-lto-objects compilation failed to produce executable UNRESOLVED: gcc.dg/vect/vect-widen-mult-half.c compilation failed to produce executable Which are all due to a bad uaddw2 instruction being emitted: uaddw2 v26.4s, v31.4s, v26.4h Thanks, Andrew Pinski > > > They all should be `scan-assembler-times`. > > Thanks, > Andrew > > > > > --- inline copy of patch -- > > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aa= rch64-simd.md > > index 81ff5bad03d598fa0d48df93d172a28bc0d1d92e..3d811007dd94dcd9176d602= 1a41a196c12fe9c3f 100644 > > --- a/gcc/config/aarch64/aarch64-simd.md > > +++ b/gcc/config/aarch64/aarch64-simd.md > > @@ -1988,26 +1988,60 @@ (define_insn "aarch64_simd_vec_unpack_hi_" > > [(set_attr "type" "neon_shift_imm_long")] > > ) > > > > -(define_expand "vec_unpack_hi_" > > +(define_expand "vec_unpacku_hi_" > > [(match_operand: 0 "register_operand") > > - (ANY_EXTEND: (match_operand:VQW 1 "register_operand"))] > > + (match_operand:VQW 1 "register_operand")] > > + "TARGET_SIMD" > > + { > > + rtx res =3D gen_reg_rtx (mode); > > + rtx tmp =3D aarch64_gen_shareable_zero (mode); > > + if (BYTES_BIG_ENDIAN) > > + emit_insn (gen_aarch64_zip2 (res, tmp, operands[1])); > > + else > > + emit_insn (gen_aarch64_zip2 (res, operands[1], tmp)); > > + emit_move_insn (operands[0], > > + simplify_gen_subreg (mode, res, mode, 0= )); > > + DONE; > > + } > > +) > > + > > +(define_expand "vec_unpacks_hi_" > > + [(match_operand: 0 "register_operand") > > + (match_operand:VQW 1 "register_operand")] > > "TARGET_SIMD" > > { > > rtx p =3D aarch64_simd_vect_par_cnst_half (mode, , t= rue); > > - emit_insn (gen_aarch64_simd_vec_unpack_hi_ (operands[0], > > - operands[1], = p)); > > + emit_insn (gen_aarch64_simd_vec_unpacks_hi_ (operands[0], > > + operands[1], p))= ; > > + DONE; > > + } > > +) > > + > > +(define_expand "vec_unpacku_lo_" > > + [(match_operand: 0 "register_operand") > > + (match_operand:VQW 1 "register_operand")] > > + "TARGET_SIMD" > > + { > > + rtx res =3D gen_reg_rtx (mode); > > + rtx tmp =3D aarch64_gen_shareable_zero (mode); > > + if (BYTES_BIG_ENDIAN) > > + emit_insn (gen_aarch64_zip1 (res, tmp, operands[1])); > > + else > > + emit_insn (gen_aarch64_zip1 (res, operands[1], tmp)); > > + emit_move_insn (operands[0], > > + simplify_gen_subreg (mode, res, mode, 0= )); > > DONE; > > } > > ) > > > > -(define_expand "vec_unpack_lo_" > > +(define_expand "vec_unpacks_lo_" > > [(match_operand: 0 "register_operand") > > - (ANY_EXTEND: (match_operand:VQW 1 "register_operand"))] > > + (match_operand:VQW 1 "register_operand")] > > "TARGET_SIMD" > > { > > rtx p =3D aarch64_simd_vect_par_cnst_half (mode, , f= alse); > > - emit_insn (gen_aarch64_simd_vec_unpack_lo_ (operands[0], > > - operands[1], = p)); > > + emit_insn (gen_aarch64_simd_vec_unpacks_lo_ (operands[0], > > + operands[1], p))= ; > > DONE; > > } > > ) > > @@ -4735,6 +4769,34 @@ (define_insn "aarch64_subw2= _internal" > > [(set_attr "type" "neon_sub_widen")] > > ) > > > > +(define_insn "aarch64_usubw__zip" > > + [(set (match_operand: 0 "register_operand" "=3Dw") > > + (minus: > > + (match_operand: 1 "register_operand" "w") > > + (subreg: > > + (unspec: [ > > + (match_operand:VQW 2 "register_operand" "w") > > + (match_operand:VQW 3 "aarch64_simd_imm_zero" "Dz") > > + ] PERM_EXTEND) 0)))] > > + "TARGET_SIMD" > > + "usubw\\t%0., %1., %2." > > + [(set_attr "type" "neon_sub_widen")] > > +) > > + > > +(define_insn "aarch64_uaddw__zip" > > + [(set (match_operand: 0 "register_operand" "=3Dw") > > + (plus: > > + (subreg: > > + (unspec: [ > > + (match_operand:VQW 2 "register_operand" "w") > > + (match_operand:VQW 3 "aarch64_simd_imm_zero" "Dz") > > + ] PERM_EXTEND) 0) > > + (match_operand: 1 "register_operand" "w")))] > > + "TARGET_SIMD" > > + "uaddw\\t%0., %1., %2." > > + [(set_attr "type" "neon_add_widen")] > > +) > > + > > (define_insn "aarch64_addw" > > [(set (match_operand: 0 "register_operand" "=3Dw") > > (plus: > > diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/itera= tors.md > > index f9e2210095ea9d6d9c96971222a7757a2f418c2d..de281671aedc5141c69063f= 14cf0fbec5adecb04 100644 > > --- a/gcc/config/aarch64/iterators.md > > +++ b/gcc/config/aarch64/iterators.md > > @@ -2674,6 +2674,9 @@ (define_int_iterator PERMUTEQ [UNSPEC_ZIP1Q UNSPE= C_ZIP2Q > > (define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 > > UNSPEC_UZP1 UNSPEC_UZP2]) > > > > +;; Permutes for zero extends > > +(define_int_iterator PERM_EXTEND [UNSPEC_ZIP1 UNSPEC_ZIP2]) > > + > > (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16]) > > > > (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM > > @@ -3496,7 +3499,10 @@ (define_int_attr rev_op [(UNSPEC_REV64 "64") (UN= SPEC_REV32 "32") > > (UNSPEC_REV16 "16")]) > > > > (define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI = "hi") > > - (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "= lo")]) > > + (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "= lo") > > + (UNSPEC_ZIP2 "hi") (UNSPEC_ZIP1 "lo")]) > > + > > +(define_int_attr perm_index [(UNSPEC_ZIP2 "2") (UNSPEC_ZIP1 "")]) > > > > ;; Return true if the associated optab refers to the high-numbered lan= es, > > ;; false if it refers to the low-numbered lanes. The convention is fo= r > > diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vmovl_high_1.c b/gcc= /testsuite/gcc.target/aarch64/simd/vmovl_high_1.c > > index d45bb83e3503d512c443f37a446d30d188719a96..a2d09eaee0de5a3d3409330= c5c26a3b5315e84eb 100644 > > --- a/gcc/testsuite/gcc.target/aarch64/simd/vmovl_high_1.c > > +++ b/gcc/testsuite/gcc.target/aarch64/simd/vmovl_high_1.c > > @@ -22,11 +22,11 @@ FUNC (int32x4_t, int64x2_t, s32) > > /* { dg-final { scan-assembler-times {sxtl2\tv0\.2d, v0\.4s} 1} } */ > > > > FUNC (uint8x16_t, uint16x8_t, u8) > > -/* { dg-final { scan-assembler-times {uxtl2\tv0\.8h, v0\.16b} 1} } */ > > +/* { dg-final { scan-assembler-times {zip2\tv0\.16b, v0\.16b} 1} } */ > > > > FUNC (uint16x8_t, uint32x4_t, u16) > > -/* { dg-final { scan-assembler-times {uxtl2\tv0\.4s, v0\.8h} 1} } */ > > +/* { dg-final { scan-assembler-times {zip2\tv0\.8h, v0\.8h} 1} } */ > > > > FUNC (uint32x4_t, uint64x2_t, u32) > > -/* { dg-final { scan-assembler-times {uxtl2\tv0\.2d, v0\.4s} 1} } */ > > +/* { dg-final { scan-assembler-times {zip2\tv0\.4s, v0\.4s} 1} } */ > > > > diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-1.c b/gcc/te= stsuite/gcc.target/aarch64/uxtl-combine-1.c > > new file mode 100755 > > index 0000000000000000000000000000000000000000..68fa9a09fe55f5a72355e23= c90e781a898c5975e > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-1.c > > @@ -0,0 +1,20 @@ > > +/* { dg-do assemble } */ > > +/* { dg-options "-O3 --save-temps --param=3Dvect-epilogues-nomask=3D0"= } */ > > + > > +#pragma GCC target "+nosve" > > + > > +#define SIGN unsigned > > +#define TYPE1 char > > +#define TYPE2 short > > + > > +void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) > > +{ > > + for (int i =3D 0; i < (n & -8); i++) > > + a[i] =3D b[i]; > > +} > > + > > +/* { dg-final { scan-assembler-times {\tzip1\t} 1 } } */ > > +/* { dg-final { scan-assembler-times {\tzip2\t} 1 } } */ > > +/* { dg-final { scan-assembler-not {\tuxtl\t} } } */ > > +/* { dg-final { scan-assembler-not {\tuxtl2\t} } } */ > > + > > diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-2.c b/gcc/te= stsuite/gcc.target/aarch64/uxtl-combine-2.c > > new file mode 100755 > > index 0000000000000000000000000000000000000000..af8a89085cfca800b41970a= 8410bc91b84a31d07 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-2.c > > @@ -0,0 +1,20 @@ > > +/* { dg-do assemble } */ > > +/* { dg-options "-O3 --save-temps --param=3Dvect-epilogues-nomask=3D0"= } */ > > + > > +#pragma GCC target "+nosve" > > + > > +#define SIGN unsigned > > +#define TYPE1 short > > +#define TYPE2 int > > + > > +void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) > > +{ > > + for (int i =3D 0; i < (n & -8); i++) > > + a[i] =3D b[i]; > > +} > > + > > +/* { dg-final { scan-assembler-times {\tzip1\t} 1 } } */ > > +/* { dg-final { scan-assembler-times {\tzip2\t} 1 } } */ > > +/* { dg-final { scan-assembler-not {\tuxtl\t} } } */ > > +/* { dg-final { scan-assembler-not {\tuxtl2\t} } } */ > > + > > diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-3.c b/gcc/te= stsuite/gcc.target/aarch64/uxtl-combine-3.c > > new file mode 100755 > > index 0000000000000000000000000000000000000000..cdae6d09529b743857a092f= 53a07111df64775d7 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-3.c > > @@ -0,0 +1,20 @@ > > +/* { dg-do assemble } */ > > +/* { dg-options "-O3 --save-temps --param=3Dvect-epilogues-nomask=3D0"= } */ > > + > > +#pragma GCC target "+nosve" > > + > > +#define SIGN unsigned > > +#define TYPE1 int > > +#define TYPE2 long long > > + > > +void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) > > +{ > > + for (int i =3D 0; i < (n & -8); i++) > > + a[i] =3D b[i]; > > +} > > + > > +/* { dg-final { scan-assembler-times {\tzip1\t} 1 } } */ > > +/* { dg-final { scan-assembler-times {\tzip2\t} 1 } } */ > > +/* { dg-final { scan-assembler-not {\tuxtl\t} } } */ > > +/* { dg-final { scan-assembler-not {\tuxtl2\t} } } */ > > + > > diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-4.c b/gcc/te= stsuite/gcc.target/aarch64/uxtl-combine-4.c > > new file mode 100755 > > index 0000000000000000000000000000000000000000..e1a9c4f5661a36ec7b2c5dc= 6f0fd85c42fcaac39 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-4.c > > @@ -0,0 +1,20 @@ > > +/* { dg-do assemble } */ > > +/* { dg-options "-O3 --save-temps --param=3Dvect-epilogues-nomask=3D0"= } */ > > + > > +#pragma GCC target "+nosve" > > + > > +#define SIGN signed > > +#define TYPE1 char > > +#define TYPE2 short > > + > > +void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) > > +{ > > + for (int i =3D 0; i < (n & -8); i++) > > + a[i] =3D b[i]; > > +} > > + > > +/* { dg-final { scan-assembler-not {\tzip1\t} } } */ > > +/* { dg-final { scan-assembler-not {\tzip2\t} } } */ > > +/* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */ > > +/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */ > > + > > diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-5.c b/gcc/te= stsuite/gcc.target/aarch64/uxtl-combine-5.c > > new file mode 100755 > > index 0000000000000000000000000000000000000000..92b09ba4abba80f240ac175= be2ef880968534975 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-5.c > > @@ -0,0 +1,20 @@ > > +/* { dg-do assemble } */ > > +/* { dg-options "-O3 --save-temps --param=3Dvect-epilogues-nomask=3D0"= } */ > > + > > +#pragma GCC target "+nosve" > > + > > +#define SIGN signed > > +#define TYPE1 short > > +#define TYPE2 int > > + > > +void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) > > +{ > > + for (int i =3D 0; i < (n & -8); i++) > > + a[i] =3D b[i]; > > +} > > + > > +/* { dg-final { scan-assembler-not {\tzip1\t} } } */ > > +/* { dg-final { scan-assembler-not {\tzip2\t} } } */ > > +/* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */ > > +/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */ > > + > > diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-6.c b/gcc/te= stsuite/gcc.target/aarch64/uxtl-combine-6.c > > new file mode 100755 > > index 0000000000000000000000000000000000000000..5c6e635f29d1e52f51f5b75= a477f7d8744f32ca3 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-6.c > > @@ -0,0 +1,20 @@ > > +/* { dg-do assemble } */ > > +/* { dg-options "-O3 --save-temps --param=3Dvect-epilogues-nomask=3D0"= } */ > > + > > +#pragma GCC target "+nosve" > > + > > +#define SIGN signed > > +#define TYPE1 int > > +#define TYPE2 long long > > + > > +void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) > > +{ > > + for (int i =3D 0; i < (n & -8); i++) > > + a[i] =3D b[i]; > > +} > > + > > +/* { dg-final { scan-assembler-not {\tzip1\t} } } */ > > +/* { dg-final { scan-assembler-not {\tzip2\t} } } */ > > +/* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */ > > +/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */ > > + > > > > > > > > > > --