From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by sourceware.org (Postfix) with ESMTPS id 75464385840F for ; Fri, 24 Feb 2023 06:52:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 75464385840F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pj1-x102f.google.com with SMTP id q31-20020a17090a17a200b0023750b69614so1695235pja.5 for ; Thu, 23 Feb 2023 22:52:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=BcIUssgPMKFTDLEEA698GXnfvD+MKihSgK8BHdeRxNw=; b=avFggyew037AD2k5Zxx3N1UB+bA5XnKvaond8dsDFCzd/gjnaL+9IljAEjdbyO4JOC PQKTnsbpfuZoHM1l+yXF8w1RyDyHHS/iuduZq0Cv0QhwSjifAnU3UGAte4ic+ee71vT7 ef2L8TGr3wF3TEnJNL7M267+6UW9HHvZnzSwFWHjZdc/sMJdWD54Iidy4ctLICWUkUhp 9dxHXFqZATbB7RkmTQOs+VEEbP3HoJuL4x3gRS1VGgj+M4y5T2y0ow8nEb/TPIkBTfcu UchYAQ5pVZUfUJelqwoapFi/yNcW61BSot+4IYCl5D1y/myavAY6NGwPG+y3jhGvmBIo 2l5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BcIUssgPMKFTDLEEA698GXnfvD+MKihSgK8BHdeRxNw=; b=Roa9MA3yxLLcMqDM7b1yxvV/PGFwgYjhw8tPGPaUxSSS88bQvMVNrjMncWUlN7SnJp F0RasfH9pxGDX+tusplrR5Ied4lWjVMVdHt5u+Ft+7yFRhSM3DSMDO+Wo7B6sQytefGY kEQ69gTFN/sWwJBY/ajaCDhhd8kak/M8XjVO7WbKYfqlr01azyrwImh4Fy0JFuDaL9TO DlBBu6U3P2+JKCz5COrkkwbo8jeSZOHw1Sn31MkRn2ZHrROe3hJzb26soIPLFG+TyQMV oMT6kNlpTvTJPWMovqq52OKDr8jMn3zZMxKL3hDLyljy8PAzoFhbHD2dJkCK5cWQhlQt OYfQ== X-Gm-Message-State: AO0yUKUmkFRRgvor/PX1Yn3yheCchXFNfAXdd1lGhDargKSSnF3G+PNR +pXWyiL918MSh8qkHXi6IHtDaOaoa19bBVp5SB4= X-Google-Smtp-Source: AK7set8Vym1M8+oWYpz+78pojsiZtjMM7pRAZ9qn1a9J/c8yk9uRG9cVBJYNqb579nZI4gFLI1AeGPijBhgcl0L5CXw= X-Received: by 2002:a17:90a:d258:b0:234:1887:b46d with SMTP id o24-20020a17090ad25800b002341887b46dmr1276770pjw.8.1677221546243; Thu, 23 Feb 2023 22:52:26 -0800 (PST) MIME-Version: 1.0 References: <20230224055127.2500953-1-christoph.muellner@vrull.eu> <20230224055127.2500953-4-christoph.muellner@vrull.eu> In-Reply-To: <20230224055127.2500953-4-christoph.muellner@vrull.eu> From: Andrew Pinski Date: Thu, 23 Feb 2023 22:52:14 -0800 Message-ID: Subject: Re: [PATCH v3 03/11] riscv: thead: Add support for the XTheadBa ISA extension To: Christoph Muellner Cc: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Feb 23, 2023 at 9:55 PM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds support for the XTheadBa ISA extension. > The new INSN pattern is defined in a new file to separate > this vendor extension from the standard extensions. How does this interact with doing -march=3Drv32gc_xtheadba_zba ? Seems like it might be better handle that case correctly. I suspect these all XThreadB* extensions have a similar problem too. Thanks, Andrew Pinski > > gcc/ChangeLog: > > * config/riscv/riscv.md: Include thead.md > * config/riscv/thead.md: New file. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/xtheadba-addsl.c: New test. > > Changes in v3: > - Fix operand order for th.addsl. > > Signed-off-by: Christoph M=C3=BCllner > --- > gcc/config/riscv/riscv.md | 1 + > gcc/config/riscv/thead.md | 31 +++++++++++ > .../gcc.target/riscv/xtheadba-addsl.c | 55 +++++++++++++++++++ > 3 files changed, 87 insertions(+) > create mode 100644 gcc/config/riscv/thead.md > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 05924e9bbf1..d6c2265e9d4 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -3093,4 +3093,5 @@ (define_insn "riscv_prefetchi_" > (include "pic.md") > (include "generic.md") > (include "sifive-7.md") > +(include "thead.md") > (include "vector.md") > diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md > new file mode 100644 > index 00000000000..158e9124c3a > --- /dev/null > +++ b/gcc/config/riscv/thead.md > @@ -0,0 +1,31 @@ > +;; Machine description for T-Head vendor extensions > +;; Copyright (C) 2021-2022 Free Software Foundation, Inc. > + > +;; This file is part of GCC. > + > +;; GCC is free software; you can redistribute it and/or modify > +;; it under the terms of the GNU General Public License as published by > +;; the Free Software Foundation; either version 3, or (at your option) > +;; any later version. > + > +;; GCC is distributed in the hope that it will be useful, > +;; but WITHOUT ANY WARRANTY; without even the implied warranty of > +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +;; GNU General Public License for more details. > + > +;; You should have received a copy of the GNU General Public License > +;; along with GCC; see the file COPYING3. If not see > +;; . > + > +;; XTheadBa > + > +(define_insn "*th_addsl" > + [(set (match_operand:X 0 "register_operand" "=3Dr") > + (plus:X (ashift:X (match_operand:X 1 "register_operand" "r") > + (match_operand:QI 2 "immediate_operand" "I")) > + (match_operand:X 3 "register_operand" "r")))] > + "TARGET_XTHEADBA > + && (INTVAL (operands[2]) >=3D 0) && (INTVAL (operands[2]) <=3D 3)" > + "th.addsl\t%0,%3,%1,%2" > + [(set_attr "type" "bitmanip") > + (set_attr "mode" "")]) > diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c b/gcc/testsu= ite/gcc.target/riscv/xtheadba-addsl.c > new file mode 100644 > index 00000000000..5004735a246 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c > @@ -0,0 +1,55 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gc_xtheadba" { target { rv32 } } } */ > +/* { dg-options "-march=3Drv64gc_xtheadba" { target { rv64 } } } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ > + > +long > +test_1 (long a, long b) > +{ > + /* th.addsl aX, aX, 1 */ > + return a + (b << 1); > +} > + > +int > +foos (short *x, int n) > +{ > + /* th.addsl aX, aX, 1 */ > + return x[n]; > +} > + > +long > +test_2 (long a, long b) > +{ > + /* th.addsl aX, aX, 2 */ > + return a + (b << 2); > +} > + > +int > +fooi (int *x, int n) > +{ > + /* th.addsl aX, aX, 2 */ > + return x[n]; > +} > + > +long > +test_3 (long a, long b) > +{ > + /* th.addsl aX, aX, 3 */ > + return a + (b << 3); > +} > + > +long > +fool (long *x, int n) > +{ > + /* th.addsl aX, aX, 2 (rv32) */ > + /* th.addsl aX, aX, 3 (rv64) */ > + return x[n]; > +} > + > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]= +,a\[0-9\]+,1" 2 } } */ > + > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]= +,a\[0-9\]+,2" 3 { target { rv32 } } } } */ > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]= +,a\[0-9\]+,2" 2 { target { rv64 } } } } */ > + > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]= +,a\[0-9\]+,3" 1 { target { rv32 } } } } */ > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]= +,a\[0-9\]+,3" 2 { target { rv64 } } } } */ > -- > 2.39.2 >