From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by sourceware.org (Postfix) with ESMTPS id B59233858409 for ; Fri, 10 Feb 2023 23:18:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B59233858409 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pl1-x62e.google.com with SMTP id f6so8182181pln.12 for ; Fri, 10 Feb 2023 15:18:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=kauvMMheQ40UIhZOpwzRVXOZnNyyLsMQc4LtUXXr8YQ=; b=Yvp66qcTuD1VMXi4yigaj43TLQYrtSlR+r3Uej+WzbibvgtpzWjkOXYAOlN1g+lhDL 1y8qUYQlqorWeXe2IaeoAV03ad712TnBkFJTa1wTWQUX1rjmX9Z8wqQz5g7G6xhZVhTF ZZlHFMh7PJCib7nOk9HPIdz/Zc35HFf+nrHICkBZCHAPnuk0rTsM1QudWLtNXg9FUcKu vt/Zd2clGi6Yk5o6nhcZFp7151SNy9UuGpZPa39TH7btl0Ae0/2wUb0DjfpE395pk5rs IZ3IB3PAfbGyYye633yy4jdrLjMYoaMK5W220yNStSB96/VxdZlWBRHWzTUr+uzVPNlK sNlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=kauvMMheQ40UIhZOpwzRVXOZnNyyLsMQc4LtUXXr8YQ=; b=WPPYJitFC6slOhVw4+Q8eh4OJSUz4Mik+KqhtQZfGJPLve+bol8ZAp4Wt1cPoWyOIn yZTVHDNx3Q4ikIDw7oT5rAnCW1zlMOfrqsWApzqdKJRfRXeVAOiXpq6Xr9Mf2PaI8Um9 Qv4SSXCvHc1Vm0GeCi6j889qeagFdZFWdv+B2W/mX2yYDjpmz8pgQbcYk13MjGbvc76S OzFox/59QBYP8KK9/ggHQQYq+P4L/mDqSCRI0UYoUx/mHAEM5zkvqgRztqaS2zhVypQI hbnQ2kupDz9Pw9nQzze7bMoedZZn0qIQBtxEBmnd80upF3FQnZ6W8Y1jn5+j5ymQ5WDJ YezA== X-Gm-Message-State: AO0yUKU4ek/MmWyVgVVn2XxhQvrryxTBqscsFmhl5A5BS03Qp+b9jQKF lMsvBaVQfztrB6VImcEv4MEzn1gKm9G/VsEQMoc= X-Google-Smtp-Source: AK7set9B/5W17P7u9Ji7wVdyeFB0j4Lv2dr3EqxE31wYMufpgOTT7pxCOce5SELK5/DtWqUOpBlxs7C6ClCfS6M6j2c= X-Received: by 2002:a17:90b:34b:b0:230:ba44:3f4f with SMTP id fh11-20020a17090b034b00b00230ba443f4fmr2580930pjb.135.1676071114570; Fri, 10 Feb 2023 15:18:34 -0800 (PST) MIME-Version: 1.0 References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> <20230210224150.2801962-2-philipp.tomsich@vrull.eu> In-Reply-To: <20230210224150.2801962-2-philipp.tomsich@vrull.eu> From: Andrew Pinski Date: Fri, 10 Feb 2023 15:18:22 -0800 Message-ID: Subject: Re: [RFC PATCH v1 01/10] docs: Document a canonical RTL for a conditional-zero insns To: Philipp Tomsich Cc: gcc-patches@gcc.gnu.org, Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Feb 10, 2023 at 2:43 PM Philipp Tomsich wrote: > > On RISC-V, conditional-zero (i.e., move a register value or zero to a > destination register) instructions are part if the Zicond extension. > To support architectures that have similar constructs, we define a > canonical RTL representation that can be used in if-conversion. This is seems like worse canonical form than say: (define_insn "" [(set (match_operand:m 0 ...) (if_then_else (eq_or_ne (match_operand:m 1 ...) (const_int 0)) (match_operand:m 2 ...) (const_int 0) ))] "..." "...") (define_insn "" [(set (match_operand:m 0 ...) (if_then_else (eq_or_ne (match_operand:m 1 ...) (const_int 0)) (const_int 0) (match_operand:m 2 ...) ))] "..." "...") Why can't you use the above form instead? This is the standard way of expressing condition moves of 0. This matches even what aarch64 form is already: (define_insn "*cmov_insn" [(set (match_operand:ALLI 0 "register_operand" "=r,r,r,r,r,r,r") (if_then_else:ALLI (match_operator 1 "aarch64_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)]) (match_operand:ALLI 3 "aarch64_reg_zero_or_m1_or_1" "rZ,rZ,UsM,rZ,Ui1,UsM,Ui1") (match_operand:ALLI 4 "aarch64_reg_zero_or_m1_or_1" "rZ,UsM,rZ,Ui1,rZ,UsM,Ui1")))] "!((operands[3] == const1_rtx && operands[4] == constm1_rtx) || (operands[3] == constm1_rtx && operands[4] == const1_rtx))" ;; Final two alternatives should be unreachable, but included for completeness "..." [(set_attr "type" "csel, csel, csel, csel, csel, mov_imm, mov_imm")] ) (Which is more complex as it can handle even more than just the simple case you provide). Thanks, Andrew Pinski > +(define_insn "" > + [(set (match_operand:@var{m} 0 @dots{}) > + (and:@var{m} > + (neg:@var{m} (@var{eq_or_ne} (match_operand:@var{m} 1 @dots{}) > + (const_int 0))) > + (match_operand:@var{m} 2 @dots{})))] > + "@dots{}" > + "@dots{}") > > Signed-off-by: Philipp Tomsich > --- > > gcc/doc/md.texi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > index 7235d34c4b3..579462ea67f 100644 > --- a/gcc/doc/md.texi > +++ b/gcc/doc/md.texi > @@ -8347,6 +8347,23 @@ operand of @code{mult} is also a shift, then that is extended also. > This transformation is only applied when it can be proven that the > original operation had sufficient precision to prevent overflow. > > +@cindex @code{conditional-zero}, canonicalization of > +@item > +A machine that has an instruction that performs a conditional-zero > +operation (i.e., an instruction that moves a register value or puts 0 > +into the destination register) should specify the pattern for that > +instruction as: > +@smallexample > +(define_insn "" > + [(set (match_operand:@var{m} 0 @dots{}) > + (and:@var{m} > + (neg:@var{m} (@var{eq_or_ne} (match_operand:@var{m} 1 @dots{}) > + (const_int 0))) > + (match_operand:@var{m} 2 @dots{})))] > + "@dots{}" > + "@dots{}") > +@end smallexample > + > @end itemize > > Further canonicalization rules are defined in the function > -- > 2.34.1 >