* [Committed/AARCH64] Fix *extr_insv_lower_reg<mode> pattern
@ 2014-07-27 6:13 Andrew Pinski
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From: Andrew Pinski @ 2014-07-27 6:13 UTC (permalink / raw)
To: GCC Patches
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The problem here is that the pattern marks the second operand as a
rewrite constraint but this operand is never written to. It looks
like it was a copy and pasto.
Committed as obvious and should improve register allocation in some cases.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64.md (*extr_insv_lower_reg<mode>): Remove + from
the read only register.
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Index: config/aarch64/aarch64.md
===================================================================
--- config/aarch64/aarch64.md (revision 213089)
+++ config/aarch64/aarch64.md (working copy)
@@ -3390,7 +3390,7 @@ (define_insn "*extr_insv_lower_reg<mode>
[(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r")
(match_operand 1 "const_int_operand" "n")
(const_int 0))
- (zero_extract:GPI (match_operand:GPI 2 "register_operand" "+r")
+ (zero_extract:GPI (match_operand:GPI 2 "register_operand" "r")
(match_dup 1)
(match_operand 3 "const_int_operand" "n")))]
"!(UINTVAL (operands[1]) == 0
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2014-07-27 6:13 [Committed/AARCH64] Fix *extr_insv_lower_reg<mode> pattern Andrew Pinski
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