From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13514 invoked by alias); 18 Feb 2014 21:40:03 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 13499 invoked by uid 89); 18 Feb 2014 21:40:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-vc0-f171.google.com Received: from mail-vc0-f171.google.com (HELO mail-vc0-f171.google.com) (209.85.220.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 18 Feb 2014 21:40:02 +0000 Received: by mail-vc0-f171.google.com with SMTP id le5so13980910vcb.30 for ; Tue, 18 Feb 2014 13:40:00 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.52.99.227 with SMTP id et3mr3167505vdb.53.1392759600123; Tue, 18 Feb 2014 13:40:00 -0800 (PST) Received: by 10.58.195.199 with HTTP; Tue, 18 Feb 2014 13:40:00 -0800 (PST) In-Reply-To: <1392757787-25629-11-git-send-email-philipp.tomsich@theobroma-systems.com> References: <1392757787-25629-1-git-send-email-philipp.tomsich@theobroma-systems.com> <1392757787-25629-11-git-send-email-philipp.tomsich@theobroma-systems.com> Date: Tue, 18 Feb 2014 21:40:00 -0000 Message-ID: Subject: Re: [AArch64 10/14] Add movcc definition for GPF case. From: Andrew Pinski To: Philipp Tomsich Cc: GCC Patches Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2014-02/txt/msg01089.txt.bz2 On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich wrote: Can you add a testcase or two for this patch? Thanks, Andrew Pinski > --- > gcc/config/aarch64/aarch64.md | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index c72d123..b6453b6 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -2460,6 +2460,25 @@ > } > ) > > +(define_expand "movcc" > + [(set (match_operand:GPF 0 "register_operand" "") > + (if_then_else:GPF (match_operand 1 "aarch64_comparison_operator" "") > + (match_operand:GPF 2 "register_operand" "") > + (match_operand:GPF 3 "register_operand" "")))] > + "" > + { > + rtx ccreg; > + enum rtx_code code = GET_CODE (operands[1]); > + > + if (code == UNEQ || code == LTGT) > + FAIL; > + > + ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), > + XEXP (operands[1], 1)); > + operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); > + } > +) > + > (define_expand "movcc" > [(set (match_operand:GPI 0 "register_operand" "") > (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator" "") > -- > 1.9.0 >