From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by sourceware.org (Postfix) with ESMTPS id 861A73858291 for ; Wed, 3 Jan 2024 03:20:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 861A73858291 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 861A73858291 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::1036 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704252014; cv=none; b=Zw0yJgewsWbOaR5wWag78Qnz25BQuXf7tFe119z3aL1nsT8Sap3ygdMmFHIsZMBaf/KvRB6mQ3bCfTH9Gs7S6zat5vBnz/8xyb0lCg7GCYahE4/8XMG6LhewSSXEQGpdxgEANboJkoUg7ATP54c2Fr1NfnHox6euiOMRLSszagY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704252014; c=relaxed/simple; bh=yyQcJLtRrG8lp5Nw7cLCzz1qHC/NHEkoIGyXMmtWFzk=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=Oicixg55qvXdLS2XR9TP9SNevV0goXzHEoLzNuM7XOOo9rPCWCa/8HcHKpC3rHZsaNZVuoruropYNVHpTEBt37Ir/P7JprUP2KHcQFju0zxwEEN1skumtqQZ7Kd6SgTwm7c5hw7xhFmamddAxKGWIIWTMD8u6P/gTUJuxP29c18= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-28b400f08a4so7764229a91.1 for ; Tue, 02 Jan 2024 19:20:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704252011; x=1704856811; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=Qk6o0VgFwSxA6NPcDGRrk2Sesx1YYVubRbR5FPMYEEY=; b=dClmh5uqupd1MlXMEIADfOrpNKHqxOFGNlCYicP355AJ6OgEn3cWVIsVNc5S859VRP 4otJNnk21pQzHATYQ9Gyj28abdjRAF1l6Nqme4Q9P0nNTB1i7081sSwUJB2GB7p/0iNW Iw0JX4GLqASLh6iyDkifpkDE3ADDc1VGl/SLhtNZN55I0SDQmb3iztYRZzrva8DUACB3 wID//nHUAqZRL+/Zzx+RPyC3dYgYZJh786bYAbKjsZ0DI3aJc98vf2rCebC7c7+O9AcQ EnClG6rnMQa6zBU/haqyWxyEXaT9cDvLpX9F9P6rfT0i3liasUEYfXeth7cPsWPLKqVh p5TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704252011; x=1704856811; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qk6o0VgFwSxA6NPcDGRrk2Sesx1YYVubRbR5FPMYEEY=; b=cGcy+LdMYL3/06s4V1qj3WITMaKv1N98x7bXxe/PvVwBarmIMdmbsfTU/BNEeFTK3e Bqj0sQP7+CHLlagYSMTAcklKCv5wSdTxlsYp+62+bJ2/IovqtN0f8N3N2BBsvwsx5Yji M13uLJr5DZc3YxYU4iilhWugj506aQuwbF/vZwZmKV804ZGPiju0mWiom5bI2Ah4ze+R 6xx775U71FSzYjzMOSfattD2s9Bov2S+LRTrU4Ed9XX+FSsvC56peq85QOFqUNs9RW6y Y4ndrE+YiL1jtkg8k+6m0y8e1pJJKjBPBxTFLIcESF7U23YYhdur6vi/A14xxVSH0FJ5 8j3Q== X-Gm-Message-State: AOJu0Yx1g7bip7mZLhsvt7l5603qXcqddQUz4bqlVTXszKfishJ+yDgq 9lWCz6XF4GIWIeteP/1B7u9UlZHbejQbg6urnIFFDV7ye0E= X-Google-Smtp-Source: AGHT+IHisV3SE0UJDv8HhODjEdQnI3pmyPQ1WO4rWYK+teGZfW50sSsr1pQVk0EFrmLm/8K7+bSL2rYnkEO0uUAAyC4= X-Received: by 2002:a17:90a:d90b:b0:28c:be67:2e88 with SMTP id c11-20020a17090ad90b00b0028cbe672e88mr2320694pjv.47.1704252011461; Tue, 02 Jan 2024 19:20:11 -0800 (PST) MIME-Version: 1.0 References: <20231229040310.1047-1-cooper.joshua@linux.alibaba.com> <20231229041943.1366-1-cooper.joshua@linux.alibaba.com> <929ccf06-d106-40a5-b5b3-050d5aaf4875@gmail.com> <27476D48F2EA4552+2024010311063870318327@rivai.ai> In-Reply-To: <27476D48F2EA4552+2024010311063870318327@rivai.ai> From: Andrew Pinski Date: Tue, 2 Jan 2024 19:19:59 -0800 Message-ID: Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector. To: "juzhe.zhong@rivai.ai" Cc: jeffreyalaw , "cooper.joshua" , gcc-patches , Jim Wilson , palmer , andrew , "philipp.tomsich" , "christoph.muellner" , jinma , "cooper.qu" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Jan 2, 2024 at 7:07=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > We have no choice. You should know theadvector is totally unrelated with = RVV1.0 standard ISA. > > Adding `%^' which missing totally unrelated ISA makes no sens to me. No, it implements it in a different way. Basically all of the patterns which are supported get changed to be instead of "v*" becomes instead "%^v" and then you change riscv_print_operand_punct_valid_p to allow '^' and then you add '^' support to riscv_print_operand (like '~' is handled there). And the next patch adds a few more '%' to support printing different different strings based on XTheadVector or not. This is how almost all other targets handle this kind of things instead of hacking ASM_OUTPUT_OPCODE . Thanks, Andrew Pinski > > ________________________________ > juzhe.zhong@rivai.ai > > > From: Andrew Pinski > Date: 2024-01-03 10:54 > To: =E9=92=9F=E5=B1=85=E5=93=B2 > CC: Jeff Law; cooper.joshua; gcc-patches; jim.wilson.gcc; palmer; andrew;= philipp.tomsich; Christoph M=C3=BCllner; jinma; Cooper Qu > Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instruc= tions of XTheadVector. > On Mon, Jan 1, 2024 at 2:59=E2=80=AFPM =E9=92=9F=E5=B1=85=E5=93=B2 wrote: > > > > This is Ok from my side. > > But before commit this patch, I think we need this patch first: > > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html > > > > I will be back to work so I will take a look at other patches today. > > > Note I hate it. It would be better if you use something like `%^' (see > `~` for an example of how that works) instead of hacking > riscv_asm_output_opcode really. In fact that is how other targets > implement this kind of things. > > Thanks, > Andrew PInski > > > ________________________________ > > juzhe.zhong@rivai.ai > > > > > > From: Jeff Law > > Date: 2024-01-01 01:43 > > To: Jun Sha (Joshua); gcc-patches > > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner= ; juzhe.zhong; Jin Ma; Xianmiao Qu > > Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructi= ons of XTheadVector. > > > > > > On 12/28/23 21:19, Jun Sha (Joshua) wrote: > > > This patch adds th. prefix to all XTheadVector instructions by > > > implementing new assembly output functions. We only check the > > > prefix is 'v', so that no extra attribute is needed. > > > > > > gcc/ChangeLog: > > > > > > * config/riscv/riscv-protos.h (riscv_asm_output_opcode): > > > New function to add assembler insn code prefix/suffix. > > > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise. > > > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise. > > > > > > Co-authored-by: Jin Ma > > > Co-authored-by: Xianmiao Qu > > > Co-authored-by: Christoph M=C3=BCllner > > > --- > > > gcc/config/riscv/riscv-protos.h | 1 + > > > gcc/config/riscv/riscv.cc | 14 +++++++++++= +++ > > > gcc/config/riscv/riscv.h | 4 ++++ > > > .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 +++++++++++= + > > > 4 files changed, 31 insertions(+) > > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/= prefix.c > > > > > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv= -protos.h > > > index 31049ef7523..5ea54b45703 100644 > > > --- a/gcc/config/riscv/riscv-protos.h > > > +++ b/gcc/config/riscv/riscv-protos.h > > > @@ -102,6 +102,7 @@ struct riscv_address_info { > > > }; > > > > > > /* Routines implemented in riscv.cc. */ > > > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, cons= t char *p); > > > extern enum riscv_symbol_type riscv_classify_symbolic_expression (r= tx); > > > extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type = *); > > > extern int riscv_float_const_rtx_index_for_fli (rtx); > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > > index 0d1cbc5cb5f..ea1d59d9cf2 100644 > > > --- a/gcc/config/riscv/riscv.cc > > > +++ b/gcc/config/riscv/riscv.cc > > > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode= ) > > > return lmul; > > > } > > > > > > +/* Define ASM_OUTPUT_OPCODE to do anything special before > > > + emitting an opcode. */ > > > +const char * > > > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p) > > > +{ > > > + /* We need to add th. prefix to all the xtheadvector > > > + insturctions here.*/ > > > + if (TARGET_XTHEADVECTOR && current_output_insn !=3D NULL_RTX && > > > + p[0] =3D=3D 'v') > > > + fputs ("th.", asm_out_file); > > > + > > > + return p; > > Just a formatting nit. The GNU standards break lines before the > > operator, not after. So > > if (TARGET_XTHEADVECTOR > > && current_output_insn !=3D NULL > > && p[0] =3D=3D 'v') > > > > Note that current_output_insn is "extern rtx_insn *", so use NULL, not > > NULL_RTX. > > > > Neither of these nits require a new version for review. Just fix them. > > > > If Juzhe is fine with this, so am I. We can refine it if necessary lat= er. > > > > jeff > > >