From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24182 invoked by alias); 18 Feb 2014 21:42:33 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 24172 invoked by uid 89); 18 Feb 2014 21:42:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ve0-f177.google.com Received: from mail-ve0-f177.google.com (HELO mail-ve0-f177.google.com) (209.85.128.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 18 Feb 2014 21:42:31 +0000 Received: by mail-ve0-f177.google.com with SMTP id jz11so13978847veb.36 for ; Tue, 18 Feb 2014 13:42:29 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.52.24.101 with SMTP id t5mr64312vdf.79.1392759749786; Tue, 18 Feb 2014 13:42:29 -0800 (PST) Received: by 10.58.195.199 with HTTP; Tue, 18 Feb 2014 13:42:29 -0800 (PST) In-Reply-To: <1392757787-25629-10-git-send-email-philipp.tomsich@theobroma-systems.com> References: <1392757787-25629-1-git-send-email-philipp.tomsich@theobroma-systems.com> <1392757787-25629-10-git-send-email-philipp.tomsich@theobroma-systems.com> Date: Tue, 18 Feb 2014 21:42:00 -0000 Message-ID: Subject: Re: [AArch64 09/14] Add special cases of zero-extend w/ compare operations. From: Andrew Pinski To: Philipp Tomsich Cc: GCC Patches Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2014-02/txt/msg01092.txt.bz2 On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich wrote: Can you add a testcase or two for this patch? Having an example will help people in the future understand why these patterns are added. Thanks, Andrew Pinski > --- > gcc/config/aarch64/aarch64.md | 56 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 56 insertions(+) > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 60e42af..c72d123 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -2227,6 +2227,62 @@ > [(set_attr "type" "alus_ext")] > ) > > +(define_insn "*zextqi3_compare0" > + [(set (reg:CC_ZESWP CC_REGNUM) > + (compare:CC_ZESWP > + (zero_extend:GPI (match_operand:QI 1 "register_operand" "r")) > + (const_int 0))) > + (set (match_operand:GPI 0 "register_operand" "=r") > + (zero_extend:GPI (match_dup 1)))] > + "" > + "ands\\t%0, %1, 0xFF" > + [(set_attr "type" "logics_imm")] > +) > + > +(define_insn "*zexthi3_compare0" > + [(set (reg:CC_ZESWP CC_REGNUM) > + (compare:CC_ZESWP > + (zero_extend:GPI (match_operand:HI 1 "register_operand" "r")) > + (const_int 0))) > + (set (match_operand:GPI 0 "register_operand" "=r") > + (zero_extend:GPI (match_dup 1)))] > + "" > + "ands\\t%0, %1, 0xFFFF" > + [(set_attr "type" "logics_imm")] > +) > + > +(define_insn "*zextdisi3_compare0" > + [(set (reg:CC_ZESWP CC_REGNUM) > + (compare:CC_ZESWP > + (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) > + (const_int 0))) > + (set (match_operand:DI 0 "register_operand" "=r") > + (zero_extend:DI (match_dup 1)))] > + "" > + "ands\\t%x0, %x1, 0xFFFFFFFF" > + [(set_attr "type" "logics_imm")] > +) > + > +(define_insn "*zextqi3nr_compare0" > + [(set (reg:CC_ZESWP CC_REGNUM) > + (compare:CC_ZESWP > + (match_operand:QI 0 "register_operand" "r") > + (const_int 0)))] > + "" > + "tst\\t%w0, 0xFF" > + [(set_attr "type" "logics_imm")] > +) > + > +(define_insn "*zexthi3nr_compare0" > + [(set (reg:CC_ZESWP CC_REGNUM) > + (compare:CC_ZESWP > + (match_operand:HI 0 "register_operand" "r") > + (const_int 0)))] > + "" > + "tst\\t%w0, 0xFFFF" > + [(set_attr "type" "logics_imm")] > +) > + > ;; ------------------------------------------------------------------- > ;; Store-flag and conditional select insns > ;; ------------------------------------------------------------------- > -- > 1.9.0 >