From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by sourceware.org (Postfix) with ESMTPS id E98583858CDA; Fri, 30 Dec 2022 08:30:17 +0000 (GMT) Received: by mail-pj1-x102a.google.com with SMTP id fy4so21697215pjb.0; Fri, 30 Dec 2022 00:30:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=oglUL4d+sf15YRqrX3GwgFzzDseP6BD180UPNGWjJps=; b=SUCJS5sDN8VWremRxzhjeg1aVZC7bR6w1qHkopSG1PdvUGpeSWR10gJAXt2Txvl+2N 1fGGKPq/CTZ8tCFaqEhTLB4mprg8htiKypHNoWgc79sxJqRvriQxwhMCt/SjagQNerW2 eOCXknIgUVczVIpaRmdjbJ3IJVH/b5xpSKKv97Tv51NIWnkDvTiWpfsFAVsxjk1RJ7CC CouTCubTQaPlRL/c6fPiISEvWin/ts2iVkEQNzVteSBdUXaxj28tiMyCziX8QpZnKVSu E7hyuiaIBbWOyQLsFReuM9jTewSNeoRxNvO9IROHyHfxz95k5HcJoQW0z8cTThnSXSDa YDYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=oglUL4d+sf15YRqrX3GwgFzzDseP6BD180UPNGWjJps=; b=36/tm+gmD+Ix4wIPTxOMYn/51vZPDbDPyt5Fus7py6OqzxPJy6aW03YtuQ4EaAXDtb eW9GM9DHF6yrhduL3kym0wYo3jIvU35573eBgmDoSauLbAoxx5/bL12KYfNa2gGEJ/01 qojs6ymxP/xor1Ka1DA3Q//mIC0JHIoPAroIY8+GfADWmkvMA4xkqyNEbVBSIUolz1Xr 77q41EGajZCIWOt+nCr0LcIiiI+bH8rLXhjOh2ywOcuaxGyJ6jfbiuwua69lN6ae6xLr kJdVil0QuI9DqJeMKviuHe6vXvvRuylAArp/kcmEeyzgrehLdDUajJXEXQIvpPlvcBQD bB3Q== X-Gm-Message-State: AFqh2krWMZfKwI6HBQkBphaczwrsTyW6K5Wp6IAk/SmmJ8LSz7ngz65L 5X6J2h5veaDhxGhidCAtfpWruCJ1rInXObqW/TA= X-Google-Smtp-Source: AMrXdXuJOzHITSiAtY9TNLbs4gK1zNtAdERl935i91sMl5gIgGFaREW6Htsaa/0r2FbtOPNWCLzAeNfCHO7sdlMpVU4= X-Received: by 2002:a17:90a:df83:b0:219:f8ee:c7fc with SMTP id p3-20020a17090adf8300b00219f8eec7fcmr2943529pjv.163.1672389016854; Fri, 30 Dec 2022 00:30:16 -0800 (PST) MIME-Version: 1.0 References: <20221223165239.GA25951@gate.crashing.org> <20221223195207.GB25951@gate.crashing.org> <7ek02dft05.fsf@pike.rch.stglabs.ibm.com> <7e8ritexu0.fsf@pike.rch.stglabs.ibm.com> <7epmc1eil4.fsf@pike.rch.stglabs.ibm.com> <20221230074419.GE25951@gate.crashing.org> In-Reply-To: <20221230074419.GE25951@gate.crashing.org> From: Andrew Pinski Date: Fri, 30 Dec 2022 00:30:04 -0800 Message-ID: Subject: Re: [PATCH] loading float member of parameter stored via int registers To: Segher Boessenkool Cc: Jiufu Guo , Jiufu Guo via Gcc-patches , Richard Biener , Richard Biener , dje.gcc@gmail.com, linkw@gcc.gnu.org, jeffreyalaw@gmail.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Dec 29, 2022 at 11:45 PM Segher Boessenkool wrote: > > Hi! > > On Fri, Dec 30, 2022 at 10:22:31AM +0800, Jiufu Guo wrote: > > Considering the limitations of CSE, I try to find other places > > to handle this issue, and notice DSE can optimize below code: > > "[sfp:DI]=x:DI ; y:SI=[sfp:DI]" to "y:SI=x:DI#0". > > > > So, I drafted a patch to update DSE to handle DI->DF/SF. > > The patch updates "extract_low_bits" to get mode change > > with subreg. > > > > diff --git a/gcc/expmed.cc b/gcc/expmed.cc > > index b12b0e000c2..5e36331082c 100644 > > --- a/gcc/expmed.cc > > +++ b/gcc/expmed.cc > > @@ -2439,7 +2439,10 @@ extract_low_bits (machine_mode mode, machine_mode src_mode, rtx src) > > > > if (!targetm.modes_tieable_p (src_int_mode, src_mode)) > > return NULL_RTX; > > - if (!targetm.modes_tieable_p (int_mode, mode)) > > + if (!targetm.modes_tieable_p (int_mode, mode) > > + && !(known_le (GET_MODE_BITSIZE (mode), GET_MODE_BITSIZE (src_mode)) > > + && GET_MODE_CLASS (mode) == MODE_FLOAT > > + && GET_MODE_CLASS (src_mode) == MODE_INT)) > > return NULL_RTX; > > > > src = gen_lowpart (src_int_mode, src); > > Ah! This simply shows rs6000_modes_tieable_p is decidedly non-optimal: > it does not allow tying a scalar float to anything else. No such thing > is required, or good apparently. I wonder why we have such restrictions > at all in rs6000; is it just unfortunate history, was it good at one > point in time? The documentation for TARGET_MODES_TIEABLE_P says the following: If TARGET_HARD_REGNO_MODE_OK (r, mode1) and TARGET_HARD_REGNO_MODE_OK (r, mode2) are always the same for any r, then TARGET_MODES_TIEABLE_P (mode1, mode2) should be true. If they differ for any r, you should define this hook to return false unless some other mechanism ensures the accessibility of the value in a narrower mode. even though rs6000_hard_regno_mode_ok_uncached's comment has the following: /* The float registers (except for VSX vector modes) can only hold floating modes and DImode. */ TARGET_P8_VECTOR and TARGET_P9_VECTOR has special cased different modes now: if (TARGET_P8_VECTOR && (mode == SImode)) return 1; if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode)) return 1; Which I suspect that means rs6000_modes_tieable_p should return true for SImode and SFmode if TARGET_P8_VECTOR is true. Likewise for TARGET_P9_VECTOR and SFmode and QImode/HImode too. Thanks, Andrew Pinski > > > Segher