From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by sourceware.org (Postfix) with ESMTPS id 94E553882174 for ; Tue, 21 Nov 2023 22:44:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 94E553882174 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 94E553882174 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::436 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700606648; cv=none; b=DyoxAbvwlk8L56d+wMSduF9AU6XO05ZtXFNx9WQSC+Kkklm0TbWCeqGoubw7d1FbudQowFyNxZ6fAjaKx8aBkCu5FWMVgZJsYBuX71luarLc1C42yKSviaM5dIB00VPWVmLHIGe+EGSiSYW0iDbUWJeJJNUnt+zMMcCqtJRHscY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700606648; c=relaxed/simple; bh=07Wi7SYfKFQD5DfEy4dEE8X7elVIE8NH9Am/RX4ewZQ=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=B2jop9tHj7q31btGiMJOE/G2tmKOjxXoUtzxBO0ZyxHX0/URnJdKubey7V5jsZFkjUmxMhVTZwDq2kruwHcpdEBrQgJbBFXDY3gJ/mDsiXfkXR30rXRQ5FP5oCaqdAoRVWaTVMnRM/Iif2rFN9+f/3+Is4c7H0yxmfBzXd8CENE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6c4cf0aea06so5813538b3a.0 for ; Tue, 21 Nov 2023 14:44:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700606644; x=1701211444; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=lOs1NYbulxld9dDXDVS4d3b8OscDgPGH+FcBJS64REg=; b=QtEXLUScFjvusJdjU3sHKBraHdrulWCOpcBkgHnBPx8I4eIZKSlQuJUAFuzx6KkOvN 9jvRWVUOY2aYilePgRCayXwN8+xH3r5drRpEPpebRYbbz4dp9N4CsQSOV5xxGpulYLgo 3MzjDFjcJlbYKl73fdrOL24EBKdCoRJbXMOR+xm7cqOVF6irPSgo71PYtXRxBIvuNczG FbNE7EN4G4apB2NYWgaediISLiiCJGZEU7jbhY+DDah3+HIc7gTy7YDDwVNS5i3G8OL7 fuJBCaS10yJTKttyuMzFcqPT5j86M4vcrVBPGMoNenq5Qb2A+QxItqp+JtDbnnIWvchm Axtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700606644; x=1701211444; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lOs1NYbulxld9dDXDVS4d3b8OscDgPGH+FcBJS64REg=; b=RWrYnfW+68bfZk5dKLnxoX2c8SN0xKfDI24F5B9CePZVLcBQBs0DUrHF/gO0HmoB98 tqlxW6A3gfPY2fIDgw0oAKuKyndU5K8TjHB923hBWiq2ostiWrXVShSkrHIlcQrPyKtN HxeeW35UShCNrl/Uzwk07Z8FR02u7ReYaKqqfFs9QD0jI9nEfgZde8ryR2BO4gHJjlcN lDJLcslsFIT0JhH+b+y3xtLQO0KUb2qpod4ZBB0utCr5XLVkv/tS2z0EIJT0oPNLEoJw qyCDGHJnsOAEhNdeBCtHsvz7j2IaUWXa/9Igxpq3fKhH/UjSwyGO6Iw33ju+CjH94uMc anjQ== X-Gm-Message-State: AOJu0YxtG4/QtT6iLmK8gM2/4Pd3mDZMKr+nemobTkmMTqk0ZTO11e+7 FBP2iXkGCG7n4RZTw8ZaYa6mD/vqwrk1I8AKQFM= X-Google-Smtp-Source: AGHT+IF+y5vRNOWOS2tlROLjQxoUUpwATL5GljkM1DMQBBN/x7bwYd3ECCF9Vp66qYaViiyjRaXa5i2x0iptatfa+xs= X-Received: by 2002:a05:6a20:748e:b0:186:58d6:ca65 with SMTP id p14-20020a056a20748e00b0018658d6ca65mr542307pzd.32.1700606644371; Tue, 21 Nov 2023 14:44:04 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Andrew Pinski Date: Tue, 21 Nov 2023 14:43:52 -0800 Message-ID: Subject: Re: [PATCH]AArch64 Add pattern for unsigned widenings (uxtl) to zip{1,2} To: Tamar Christina Cc: gcc-patches@gcc.gnu.org, nd@arm.com, Richard.Earnshaw@arm.com, Marcus.Shawcroft@arm.com, Kyrylo.Tkachov@arm.com, richard.sandiford@arm.com, "Andrew Pinski (QUIC)" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_LOTSOFHASH,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Nov 15, 2023 at 6:42=E2=80=AFAM Tamar Christina wrote: > > Hi All, > > This changes unpack instructions to use zip{1,2} when doing a zero-extend= ing > widening operation. Permutes generally have a higher throughput than the > widening operations. Zeros are shuffled into the top half of the register= s. > > The testcase > > void d2 (unsigned * restrict a, unsigned short *b, int n) > { > for (int i =3D 0; i < (n & -8); i++) > a[i] =3D b[i]; > } > > now generates: > > movi v1.4s, 0 > .L3: > ldr q0, [x1], 16 > zip1 v2.8h, v0.8h, v1.8h > zip2 v0.8h, v0.8h, v1.8h > stp q2, q0, [x0] > add x0, x0, 32 > cmp x1, x2 > bne .L3 > > > instead of: > > .L3: > ldr q0, [x1], 16 > uxtl v1.4s, v0.4h > uxtl2 v0.4s, v0.8h > stp q1, q0, [x0] > add x0, x0, 32 > cmp x1, x2 > bne .L3 > > Since we need the extra 0 register we do this only for the vectorizer's l= o/hi > pairs when we know the 0 will be floated outside of the loop. > > This gives an 8% speed-up in Imagick in SPECCPU 2017 on Neoverse V2. > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > Ok for master? > > Thanks, > Tamar > > gcc/ChangeLog: > > * config/aarch64/aarch64-simd.md (vec_unpack_lo_ vec_unpack_lo_ (vec_unpacku_lo_ vec_unpacku_lo_ (aarch64_usubw__zip): New. > (aarch64_uaddw__zip): New. > * config/aarch64/iterators.md (PERM_EXTEND, perm_index): New. > (perm_hilo): Add UNSPEC_ZIP1, UNSPEC_ZIP2. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/simd/vmovl_high_1.c: Update codegen. > * gcc.target/aarch64/uxtl-combine-1.c: New test. > * gcc.target/aarch64/uxtl-combine-2.c: New test. > * gcc.target/aarch64/uxtl-combine-3.c: New test. > * gcc.target/aarch64/uxtl-combine-4.c: New test. > * gcc.target/aarch64/uxtl-combine-5.c: New test. > * gcc.target/aarch64/uxtl-combine-6.c: New test. You have a few typos in the testcases which causes: ERROR: gcc.target/aarch64/uxtl-combine-4.c: error executing dg-final: invalid command name "scan-assembler-time" ERROR: gcc.target/aarch64/uxtl-combine-5.c: error executing dg-final: invalid command name "scan-assembler-time" ERROR: gcc.target/aarch64/uxtl-combine-6.c: error executing dg-final: invalid command name "scan-assembler-time" They all should be `scan-assembler-times`. Thanks, Andrew > > --- inline copy of patch -- > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarc= h64-simd.md > index 81ff5bad03d598fa0d48df93d172a28bc0d1d92e..3d811007dd94dcd9176d6021a= 41a196c12fe9c3f 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -1988,26 +1988,60 @@ (define_insn "aarch64_simd_vec_unpack_hi_" > [(set_attr "type" "neon_shift_imm_long")] > ) > > -(define_expand "vec_unpack_hi_" > +(define_expand "vec_unpacku_hi_" > [(match_operand: 0 "register_operand") > - (ANY_EXTEND: (match_operand:VQW 1 "register_operand"))] > + (match_operand:VQW 1 "register_operand")] > + "TARGET_SIMD" > + { > + rtx res =3D gen_reg_rtx (mode); > + rtx tmp =3D aarch64_gen_shareable_zero (mode); > + if (BYTES_BIG_ENDIAN) > + emit_insn (gen_aarch64_zip2 (res, tmp, operands[1])); > + else > + emit_insn (gen_aarch64_zip2 (res, operands[1], tmp)); > + emit_move_insn (operands[0], > + simplify_gen_subreg (mode, res, mode, 0))= ; > + DONE; > + } > +) > + > +(define_expand "vec_unpacks_hi_" > + [(match_operand: 0 "register_operand") > + (match_operand:VQW 1 "register_operand")] > "TARGET_SIMD" > { > rtx p =3D aarch64_simd_vect_par_cnst_half (mode, , tru= e); > - emit_insn (gen_aarch64_simd_vec_unpack_hi_ (operands[0], > - operands[1], p)= ); > + emit_insn (gen_aarch64_simd_vec_unpacks_hi_ (operands[0], > + operands[1], p)); > + DONE; > + } > +) > + > +(define_expand "vec_unpacku_lo_" > + [(match_operand: 0 "register_operand") > + (match_operand:VQW 1 "register_operand")] > + "TARGET_SIMD" > + { > + rtx res =3D gen_reg_rtx (mode); > + rtx tmp =3D aarch64_gen_shareable_zero (mode); > + if (BYTES_BIG_ENDIAN) > + emit_insn (gen_aarch64_zip1 (res, tmp, operands[1])); > + else > + emit_insn (gen_aarch64_zip1 (res, operands[1], tmp)); > + emit_move_insn (operands[0], > + simplify_gen_subreg (mode, res, mode, 0))= ; > DONE; > } > ) > > -(define_expand "vec_unpack_lo_" > +(define_expand "vec_unpacks_lo_" > [(match_operand: 0 "register_operand") > - (ANY_EXTEND: (match_operand:VQW 1 "register_operand"))] > + (match_operand:VQW 1 "register_operand")] > "TARGET_SIMD" > { > rtx p =3D aarch64_simd_vect_par_cnst_half (mode, , fal= se); > - emit_insn (gen_aarch64_simd_vec_unpack_lo_ (operands[0], > - operands[1], p)= ); > + emit_insn (gen_aarch64_simd_vec_unpacks_lo_ (operands[0], > + operands[1], p)); > DONE; > } > ) > @@ -4735,6 +4769,34 @@ (define_insn "aarch64_subw2_i= nternal" > [(set_attr "type" "neon_sub_widen")] > ) > > +(define_insn "aarch64_usubw__zip" > + [(set (match_operand: 0 "register_operand" "=3Dw") > + (minus: > + (match_operand: 1 "register_operand" "w") > + (subreg: > + (unspec: [ > + (match_operand:VQW 2 "register_operand" "w") > + (match_operand:VQW 3 "aarch64_simd_imm_zero" "Dz") > + ] PERM_EXTEND) 0)))] > + "TARGET_SIMD" > + "usubw\\t%0., %1., %2." > + [(set_attr "type" "neon_sub_widen")] > +) > + > +(define_insn "aarch64_uaddw__zip" > + [(set (match_operand: 0 "register_operand" "=3Dw") > + (plus: > + (subreg: > + (unspec: [ > + (match_operand:VQW 2 "register_operand" "w") > + (match_operand:VQW 3 "aarch64_simd_imm_zero" "Dz") > + ] PERM_EXTEND) 0) > + (match_operand: 1 "register_operand" "w")))] > + "TARGET_SIMD" > + "uaddw\\t%0., %1., %2." > + [(set_attr "type" "neon_add_widen")] > +) > + > (define_insn "aarch64_addw" > [(set (match_operand: 0 "register_operand" "=3Dw") > (plus: > diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterato= rs.md > index f9e2210095ea9d6d9c96971222a7757a2f418c2d..de281671aedc5141c69063f14= cf0fbec5adecb04 100644 > --- a/gcc/config/aarch64/iterators.md > +++ b/gcc/config/aarch64/iterators.md > @@ -2674,6 +2674,9 @@ (define_int_iterator PERMUTEQ [UNSPEC_ZIP1Q UNSPEC_= ZIP2Q > (define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 > UNSPEC_UZP1 UNSPEC_UZP2]) > > +;; Permutes for zero extends > +(define_int_iterator PERM_EXTEND [UNSPEC_ZIP1 UNSPEC_ZIP2]) > + > (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16]) > > (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM > @@ -3496,7 +3499,10 @@ (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSP= EC_REV32 "32") > (UNSPEC_REV16 "16")]) > > (define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "h= i") > - (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo= ")]) > + (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo= ") > + (UNSPEC_ZIP2 "hi") (UNSPEC_ZIP1 "lo")]) > + > +(define_int_attr perm_index [(UNSPEC_ZIP2 "2") (UNSPEC_ZIP1 "")]) > > ;; Return true if the associated optab refers to the high-numbered lanes= , > ;; false if it refers to the low-numbered lanes. The convention is for > diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vmovl_high_1.c b/gcc/t= estsuite/gcc.target/aarch64/simd/vmovl_high_1.c > index d45bb83e3503d512c443f37a446d30d188719a96..a2d09eaee0de5a3d3409330c5= c26a3b5315e84eb 100644 > --- a/gcc/testsuite/gcc.target/aarch64/simd/vmovl_high_1.c > +++ b/gcc/testsuite/gcc.target/aarch64/simd/vmovl_high_1.c > @@ -22,11 +22,11 @@ FUNC (int32x4_t, int64x2_t, s32) > /* { dg-final { scan-assembler-times {sxtl2\tv0\.2d, v0\.4s} 1} } */ > > FUNC (uint8x16_t, uint16x8_t, u8) > -/* { dg-final { scan-assembler-times {uxtl2\tv0\.8h, v0\.16b} 1} } */ > +/* { dg-final { scan-assembler-times {zip2\tv0\.16b, v0\.16b} 1} } */ > > FUNC (uint16x8_t, uint32x4_t, u16) > -/* { dg-final { scan-assembler-times {uxtl2\tv0\.4s, v0\.8h} 1} } */ > +/* { dg-final { scan-assembler-times {zip2\tv0\.8h, v0\.8h} 1} } */ > > FUNC (uint32x4_t, uint64x2_t, u32) > -/* { dg-final { scan-assembler-times {uxtl2\tv0\.2d, v0\.4s} 1} } */ > +/* { dg-final { scan-assembler-times {zip2\tv0\.4s, v0\.4s} 1} } */ > > diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-1.c b/gcc/test= suite/gcc.target/aarch64/uxtl-combine-1.c > new file mode 100755 > index 0000000000000000000000000000000000000000..68fa9a09fe55f5a72355e23c9= 0e781a898c5975e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-1.c > @@ -0,0 +1,20 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=3Dvect-epilogues-nomask=3D0" }= */ > + > +#pragma GCC target "+nosve" > + > +#define SIGN unsigned > +#define TYPE1 char > +#define TYPE2 short > + > +void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) > +{ > + for (int i =3D 0; i < (n & -8); i++) > + a[i] =3D b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tzip1\t} 1 } } */ > +/* { dg-final { scan-assembler-times {\tzip2\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\tuxtl\t} } } */ > +/* { dg-final { scan-assembler-not {\tuxtl2\t} } } */ > + > diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-2.c b/gcc/test= suite/gcc.target/aarch64/uxtl-combine-2.c > new file mode 100755 > index 0000000000000000000000000000000000000000..af8a89085cfca800b41970a84= 10bc91b84a31d07 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-2.c > @@ -0,0 +1,20 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=3Dvect-epilogues-nomask=3D0" }= */ > + > +#pragma GCC target "+nosve" > + > +#define SIGN unsigned > +#define TYPE1 short > +#define TYPE2 int > + > +void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) > +{ > + for (int i =3D 0; i < (n & -8); i++) > + a[i] =3D b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tzip1\t} 1 } } */ > +/* { dg-final { scan-assembler-times {\tzip2\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\tuxtl\t} } } */ > +/* { dg-final { scan-assembler-not {\tuxtl2\t} } } */ > + > diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-3.c b/gcc/test= suite/gcc.target/aarch64/uxtl-combine-3.c > new file mode 100755 > index 0000000000000000000000000000000000000000..cdae6d09529b743857a092f53= a07111df64775d7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-3.c > @@ -0,0 +1,20 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=3Dvect-epilogues-nomask=3D0" }= */ > + > +#pragma GCC target "+nosve" > + > +#define SIGN unsigned > +#define TYPE1 int > +#define TYPE2 long long > + > +void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) > +{ > + for (int i =3D 0; i < (n & -8); i++) > + a[i] =3D b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tzip1\t} 1 } } */ > +/* { dg-final { scan-assembler-times {\tzip2\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\tuxtl\t} } } */ > +/* { dg-final { scan-assembler-not {\tuxtl2\t} } } */ > + > diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-4.c b/gcc/test= suite/gcc.target/aarch64/uxtl-combine-4.c > new file mode 100755 > index 0000000000000000000000000000000000000000..e1a9c4f5661a36ec7b2c5dc6f= 0fd85c42fcaac39 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-4.c > @@ -0,0 +1,20 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=3Dvect-epilogues-nomask=3D0" }= */ > + > +#pragma GCC target "+nosve" > + > +#define SIGN signed > +#define TYPE1 char > +#define TYPE2 short > + > +void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) > +{ > + for (int i =3D 0; i < (n & -8); i++) > + a[i] =3D b[i]; > +} > + > +/* { dg-final { scan-assembler-not {\tzip1\t} } } */ > +/* { dg-final { scan-assembler-not {\tzip2\t} } } */ > +/* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */ > +/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */ > + > diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-5.c b/gcc/test= suite/gcc.target/aarch64/uxtl-combine-5.c > new file mode 100755 > index 0000000000000000000000000000000000000000..92b09ba4abba80f240ac175be= 2ef880968534975 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-5.c > @@ -0,0 +1,20 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=3Dvect-epilogues-nomask=3D0" }= */ > + > +#pragma GCC target "+nosve" > + > +#define SIGN signed > +#define TYPE1 short > +#define TYPE2 int > + > +void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) > +{ > + for (int i =3D 0; i < (n & -8); i++) > + a[i] =3D b[i]; > +} > + > +/* { dg-final { scan-assembler-not {\tzip1\t} } } */ > +/* { dg-final { scan-assembler-not {\tzip2\t} } } */ > +/* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */ > +/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */ > + > diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-6.c b/gcc/test= suite/gcc.target/aarch64/uxtl-combine-6.c > new file mode 100755 > index 0000000000000000000000000000000000000000..5c6e635f29d1e52f51f5b75a4= 77f7d8744f32ca3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-6.c > @@ -0,0 +1,20 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=3Dvect-epilogues-nomask=3D0" }= */ > + > +#pragma GCC target "+nosve" > + > +#define SIGN signed > +#define TYPE1 int > +#define TYPE2 long long > + > +void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) > +{ > + for (int i =3D 0; i < (n & -8); i++) > + a[i] =3D b[i]; > +} > + > +/* { dg-final { scan-assembler-not {\tzip1\t} } } */ > +/* { dg-final { scan-assembler-not {\tzip2\t} } } */ > +/* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */ > +/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */ > + > > > > > --