From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by sourceware.org (Postfix) with ESMTPS id 0E98E3858D32 for ; Sat, 18 Feb 2023 18:43:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0E98E3858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pj1-x102b.google.com with SMTP id cn10so1308422pjb.3 for ; Sat, 18 Feb 2023 10:43:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=3KtkoyXTui/cNrxcqmcZnbALmsr/piIJFFC36mqdjuc=; b=fm0sbmSV/v3z5ozzEjpvJycSk2SvUB5MCxiJNksvgvo1CB30nVUxJcrDhjRGp8dEF1 LEADq7u3kTLJCQCBOMTSuqXV7KyBiLXjbj7F1Wi6iEenpH1VoJIabZEb6lZRlx6UNtv4 pCLvr9IEVgjJrkW01MriPDgGoorsMS57nfWRQCmnPo7uHnqI/BTQdvObp9rholPxgQGl sT8WzW3Cc0mvCU7aowOZTDq72GcNL2AlkxfOgJhkdjRLW6YCQXrmxsFuBmAfISimrJUb a9QltzieIgWoR9Ry0D0uXFhDgOxYUJEHZt/TRxqGlsbC6PO9wJS9of71IzTcgxS1M+7k MFCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=3KtkoyXTui/cNrxcqmcZnbALmsr/piIJFFC36mqdjuc=; b=GZExqAwP8xDf4r+vw7nBZSeyqRqsByr8VQrlC/Xf0MhSN6I366XgMkgDyus+JuVaAA 9LmKV4e1U37i7n6MUBZ3NFa6thruIKRgGCS/E6z69kuwveeeOZgqwHP6bl/9VvD2JUB9 HFmtVFhCQxJSa2V/zTugUoBlG8KdAjcCf6KvoV5Gl9YRMqfDsQs0wppNcflqbYA6aF5Q mpM+QrUAdLtn7Gv/oehAuHlK1xXa7bR+kgtseVMpQ1ldrwEggcXI7KEsfBgb09ThQq1x oXrDKUN2TD4suQaMDK1tNY+DQzcDq7I8rxb8GPj62Tz4xfJOS2UwQ8IQ0YZq0vKSQTiS 0h1Q== X-Gm-Message-State: AO0yUKWCiMBtBWNGC/UPBHPHT9FNUjiLchiAL/nh68Oup/Br9sSiyV5z NcNWlr0iGs+GM4kbd7nx4lL6KcnvDahG9xEYPMA= X-Google-Smtp-Source: AK7set+wE2SMNG855/pMyNIDNFsrLH0LezsfqsvzrcJJpw0yqxCzun95kWqf7NZtUcdJA86fG70apBbBcFd2k1RJvXM= X-Received: by 2002:a17:90b:1b12:b0:22c:7e3:6d9f with SMTP id nu18-20020a17090b1b1200b0022c07e36d9fmr2508650pjb.21.1676745782796; Sat, 18 Feb 2023 10:43:02 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Andrew Pinski Date: Sat, 18 Feb 2023 10:42:51 -0800 Message-ID: Subject: Re: RISC-V: Add divmod instruction support To: Palmer Dabbelt Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sat, Feb 18, 2023 at 10:27 AM Palmer Dabbelt wrote: > > On Fri, 17 Feb 2023 06:02:40 PST (-0800), gcc-patches@gcc.gnu.org wrote: > > Hi all, > > If we have division and remainder calculations with the same operands: > > > > a = b / c; > > d = b % c; > > > > We can replace the calculation of remainder with multiplication + > > subtraction, using the result from the previous division: > > > > a = b / c; > > d = a * c; > > d = b - d; > > > > Which will be faster. > > Do you have any benchmarks that show that performance increase? The ISA > manual specifically says the suggested sequence is div+mod, and while > those suggestions don't always pan out for real hardware it's likely > that at least some implementations will end up with the ISA-suggested > fusions. I suspect I will be needing this kind of patch for the core that I am going to be using. If anything this should be under a tuning option. Thanks, Andrew Pinski > > > Currently, it isn't done for RISC-V. > > > > I've added an expander for DIVMOD which replaces 'rem' with 'mul + sub'. > > > > Best regards, > > Matevos. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv.md: Added divmod expander. > > > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/divmod.c: New testcase. > > > > --- inline copy of the patch --- > > > > diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md > > index f95dd405e12..d941483d9f1 100644 > > --- a/gcc/config/riscv/iterators.md > > +++ b/gcc/config/riscv/iterators.md > > @@ -148,6 +148,11 @@ > > ;; from the same template. > > (define_code_iterator any_mod [mod umod]) > > > > +;; These code iterators allow unsigned and signed divmod to be generated > > +;; from the same template. > > +(define_code_iterator only_div [div udiv]) > > +(define_code_attr paired_mod [(div "mod") (udiv "umod")]) > > + > > ;; These code iterators allow the signed and unsigned scc operations to use > > ;; the same template. > > (define_code_iterator any_gt [gt gtu]) > > @@ -175,7 +180,8 @@ > > (gt "") (gtu "u") > > (ge "") (geu "u") > > (lt "") (ltu "u") > > - (le "") (leu "u")]) > > + (le "") (leu "u") > > + (div "") (udiv "u")]) > > > > ;; is like , but the signed form expands to "s" rather than "". > > (define_code_attr su [(sign_extend "s") (zero_extend "u")]) > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > > index c8adc5af5d2..2d48ff3f8de 100644 > > --- a/gcc/config/riscv/riscv.md > > +++ b/gcc/config/riscv/riscv.md > > @@ -1044,6 +1044,22 @@ > > [(set_attr "type" "idiv") > > (set_attr "mode" "DI")]) > > > > +(define_expand "divmod4" > > + [(parallel > > + [(set (match_operand:GPR 0 "register_operand") > > + (only_div:GPR (match_operand:GPR 1 "register_operand") > > + (match_operand:GPR 2 "register_operand"))) > > + (set (match_operand:GPR 3 "register_operand") > > + (:GPR (match_dup 1) (match_dup 2)))])] > > + "TARGET_DIV" > > + { > > + rtx tmp = gen_reg_rtx (mode); > > + emit_insn (gen_div3 (operands[0], operands[1], > > operands[2])); > > + emit_insn (gen_mul3 (tmp, operands[0], operands[2])); > > + emit_insn (gen_sub3 (operands[3], operands[1], tmp)); > > + DONE; > > + }) > > + > > (define_insn "*si3_extended" > > [(set (match_operand:DI 0 "register_operand" "=r") > > (sign_extend:DI > > diff --git a/gcc/testsuite/gcc.target/riscv/divmod.c > > b/gcc/testsuite/gcc.target/riscv/divmod.c > > new file mode 100644 > > index 00000000000..254b25e654d > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/divmod.c > > @@ -0,0 +1,14 @@ > > +/* { dg-do compile } */ > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ > > + > > +void > > +foo(int a, int b, int *c, int *d) > > +{ > > + *c = a / b; > > + *d = a % b; > > +} > > + > > +/* { dg-final { scan-assembler-not "rem" } } */ > > +/* { dg-final { scan-assembler-times "mul" 1 } } */ > > +/* { dg-final { scan-assembler-times "sub" 1 } } */