From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oo1-xc2b.google.com (mail-oo1-xc2b.google.com [IPv6:2607:f8b0:4864:20::c2b]) by sourceware.org (Postfix) with ESMTPS id 1A7263858C2A for ; Wed, 3 Jan 2024 03:32:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1A7263858C2A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1A7263858C2A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::c2b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704252752; cv=none; b=Fjy7yPJWnPlfbIn5a2xxvtTlVOUpuLQMLPnCUJ0C9vdJkmc7oTT2odU5xgJlBoSzD/IjvmsroAx65CosRXZ/Ra7sXgV0QwcuZOd+gOPiop4GMqwNqKrfqnfmgYqRX2L29DIbysn5Rlf4LTCccphfK+ag5bLrMyyP1s87ghCst0Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704252752; c=relaxed/simple; bh=TnybLOTzO/0x5qfayV1g44ZTtourArEDrbBU2NUicV0=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=e29ArypKkK/4MJMo8bCHvkkdXU0+dzbJFWJWuwUjW4cI0dHeE/jrSoaA9QAlhgR+HLjebS9ldUOtpa6Ws+VK7bDDfMQ3X9K7embIetMxBLDFEOdJKq+I58o7cPjSrJppu4CBTYoNhJ2+nj1XL8imEG3z5OHfKCUmK+VwKNNmW3U= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-oo1-xc2b.google.com with SMTP id 006d021491bc7-5953a6a00ddso1714454eaf.0 for ; Tue, 02 Jan 2024 19:32:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704252748; x=1704857548; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=pVFAx29dTF8PsWwprohb2VloV7DOUMXF5vPlhbs6WtM=; b=Q9iWL9RbdLBIX0zQYG+6oOvCBMD3LpnItcmTSt3fmP0n0tNmVutwZVJtmf9UqCF4aQ EA7HJnmcGp9Sh2trsCv8qCdIKh1cinjtu6IAx9lzjWUfhm8mGU44h1kWQ3aI0MrPu820 AB3l07mLmRSSbkYEfdX9528jLntoLNLkxo0v/ZGWU6RW8X52Xyjcx62kHBODGzfHW2GF WLpGw3XHP6Z4YH3ELhponlUsoj+8gyYL7pI7qjBZI4eD0bStoeDwhDOMBs2UUKtqb+Rm 2a9Z4tw3YMaOAGpXshWU3bnbJ+AxHnOW0ScVn0HYmgyFWYjKfLm641BXumoi60jjF9wT QV4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704252748; x=1704857548; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pVFAx29dTF8PsWwprohb2VloV7DOUMXF5vPlhbs6WtM=; b=XKDwyDNea9lyRU/IInCEL4UYLj2KWSs0IIZX44Vn2HCEQB0a0CzGwdmRDbUzhJYRvo soCL2QmMSrgpUvtcxjofCWg4+Yu6OnLtDGcbdm4UOrjYzdexyPDKfD+Sf3furFSAcstR eoHcmBXiCMd0IcXUlngbZCitvQOKCswUNm0qLwJrqf/qkS19jUS3TBXJHXPnF8OOGrlq M7nu9YYFQAPxmJuw5TU2nzp6jtfcd4HIciibSinqqD72GS48r01qkY2+DJCBD7jKUzir 9LBFl+SLD2iNVWAfWTMqmy9VdDO1yZWSeEkgW2oAqtSaSFYKozEv3eyN3L2uHb92yo7U s6dQ== X-Gm-Message-State: AOJu0YzGvDh3EpTN5dm2lthVKh5iJXjHuLtakdmVhydzT4RHY9Tyz58M MR+XjnMTGq5RWP9ArE8NlwLMdLvjt+cHqQzhhRs= X-Google-Smtp-Source: AGHT+IEFsZiQ5L2Rs1zNuRAm2bkhQ92wXBXzN05lVaezgJfHXbk21LfV5QmsXSV9KwDM8O4QFFWik+mD5v6WofuSFl4= X-Received: by 2002:a05:6358:98a7:b0:170:3ef2:de12 with SMTP id q39-20020a05635898a700b001703ef2de12mr12962616rwa.46.1704252748495; Tue, 02 Jan 2024 19:32:28 -0800 (PST) MIME-Version: 1.0 References: <20231229040310.1047-1-cooper.joshua@linux.alibaba.com> <20231229041943.1366-1-cooper.joshua@linux.alibaba.com> <929ccf06-d106-40a5-b5b3-050d5aaf4875@gmail.com> <27476D48F2EA4552+2024010311063870318327@rivai.ai> In-Reply-To: From: Andrew Pinski Date: Tue, 2 Jan 2024 19:32:17 -0800 Message-ID: Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector. To: "juzhe.zhong@rivai.ai" Cc: jeffreyalaw , "cooper.joshua" , gcc-patches , Jim Wilson , palmer , andrew , "philipp.tomsich" , "christoph.muellner" , jinma , "cooper.qu" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Jan 2, 2024 at 7:26=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > No. It will need to change all patterns in vector.md. > It's a nightmare. > > You should note I will refine vector.md in GCC-15, mixing theadvector thi= ngs make me impossible to maintain > RVV1.0. Then we should not support theadvector if things are getting this messy. Both ways are hacks really. Either way we need a better way of implementing this. Hacking theadvector support using rewriting is wrong and not maintainable either. I suspect we should wait on supporting theadvector until GCC 15 anyways. Thanks, Andrew Pinski > > ________________________________ > juzhe.zhong@rivai.ai > > > From: Andrew Pinski > Date: 2024-01-03 11:19 > To: juzhe.zhong@rivai.ai > CC: jeffreyalaw; cooper.joshua; gcc-patches; Jim Wilson; palmer; andrew; = philipp.tomsich; christoph.muellner; jinma; cooper.qu > Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instruc= tions of XTheadVector. > On Tue, Jan 2, 2024 at 7:07=E2=80=AFPM juzhe.zhong@rivai.ai > wrote: > > > > We have no choice. You should know theadvector is totally unrelated wit= h RVV1.0 standard ISA. > > > > Adding `%^' which missing totally unrelated ISA makes no sens to me. > > No, it implements it in a different way. > Basically all of the patterns which are supported get changed to be > instead of "v*" becomes instead "%^v" and then you change > riscv_print_operand_punct_valid_p to allow '^' and then you add '^' > support to riscv_print_operand (like '~' is handled there). > > And the next patch adds a few more '%' to support printing different > different strings based on XTheadVector or not. > > This is how almost all other targets handle this kind of things > instead of hacking ASM_OUTPUT_OPCODE . > > Thanks, > Andrew Pinski > > > > > > ________________________________ > > juzhe.zhong@rivai.ai > > > > > > From: Andrew Pinski > > Date: 2024-01-03 10:54 > > To: =E9=92=9F=E5=B1=85=E5=93=B2 > > CC: Jeff Law; cooper.joshua; gcc-patches; jim.wilson.gcc; palmer; andre= w; philipp.tomsich; Christoph M=C3=BCllner; jinma; Cooper Qu > > Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instr= uctions of XTheadVector. > > On Mon, Jan 1, 2024 at 2:59=E2=80=AFPM =E9=92=9F=E5=B1=85=E5=93=B2 wrote: > > > > > > This is Ok from my side. > > > But before commit this patch, I think we need this patch first: > > > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html > > > > > > I will be back to work so I will take a look at other patches today. > > > > > > Note I hate it. It would be better if you use something like `%^' (see > > `~` for an example of how that works) instead of hacking > > riscv_asm_output_opcode really. In fact that is how other targets > > implement this kind of things. > > > > Thanks, > > Andrew PInski > > > > > ________________________________ > > > juzhe.zhong@rivai.ai > > > > > > > > > From: Jeff Law > > > Date: 2024-01-01 01:43 > > > To: Jun Sha (Joshua); gcc-patches > > > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muelln= er; juzhe.zhong; Jin Ma; Xianmiao Qu > > > Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instruc= tions of XTheadVector. > > > > > > > > > On 12/28/23 21:19, Jun Sha (Joshua) wrote: > > > > This patch adds th. prefix to all XTheadVector instructions by > > > > implementing new assembly output functions. We only check the > > > > prefix is 'v', so that no extra attribute is needed. > > > > > > > > gcc/ChangeLog: > > > > > > > > * config/riscv/riscv-protos.h (riscv_asm_output_opcode): > > > > New function to add assembler insn code prefix/suffix. > > > > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise. > > > > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise. > > > > > > > > Co-authored-by: Jin Ma > > > > Co-authored-by: Xianmiao Qu > > > > Co-authored-by: Christoph M=C3=BCllner > > > > --- > > > > gcc/config/riscv/riscv-protos.h | 1 + > > > > gcc/config/riscv/riscv.cc | 14 +++++++++= +++++ > > > > gcc/config/riscv/riscv.h | 4 ++++ > > > > .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 +++++++++= +++ > > > > 4 files changed, 31 insertions(+) > > > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvecto= r/prefix.c > > > > > > > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/ris= cv-protos.h > > > > index 31049ef7523..5ea54b45703 100644 > > > > --- a/gcc/config/riscv/riscv-protos.h > > > > +++ b/gcc/config/riscv/riscv-protos.h > > > > @@ -102,6 +102,7 @@ struct riscv_address_info { > > > > }; > > > > > > > > /* Routines implemented in riscv.cc. */ > > > > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, co= nst char *p); > > > > extern enum riscv_symbol_type riscv_classify_symbolic_expression = (rtx); > > > > extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_typ= e *); > > > > extern int riscv_float_const_rtx_index_for_fli (rtx); > > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > > > index 0d1cbc5cb5f..ea1d59d9cf2 100644 > > > > --- a/gcc/config/riscv/riscv.cc > > > > +++ b/gcc/config/riscv/riscv.cc > > > > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mo= de) > > > > return lmul; > > > > } > > > > > > > > +/* Define ASM_OUTPUT_OPCODE to do anything special before > > > > + emitting an opcode. */ > > > > +const char * > > > > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p) > > > > +{ > > > > + /* We need to add th. prefix to all the xtheadvector > > > > + insturctions here.*/ > > > > + if (TARGET_XTHEADVECTOR && current_output_insn !=3D NULL_RTX && > > > > + p[0] =3D=3D 'v') > > > > + fputs ("th.", asm_out_file); > > > > + > > > > + return p; > > > Just a formatting nit. The GNU standards break lines before the > > > operator, not after. So > > > if (TARGET_XTHEADVECTOR > > > && current_output_insn !=3D NULL > > > && p[0] =3D=3D 'v') > > > > > > Note that current_output_insn is "extern rtx_insn *", so use NULL, no= t > > > NULL_RTX. > > > > > > Neither of these nits require a new version for review. Just fix the= m. > > > > > > If Juzhe is fine with this, so am I. We can refine it if necessary l= ater. > > > > > > jeff > > > > > >