From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by sourceware.org (Postfix) with ESMTPS id 7D7DE3858C2A for ; Wed, 3 Jan 2024 02:54:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7D7DE3858C2A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7D7DE3858C2A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::1031 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704250491; cv=none; b=yBm3pcIZhmF3K3HNnS4DYx10v9SBa9rrvNVOxqioU9fJS2ZVHl8oZrkMqXfY3Vn1kwDP6nwBJiB5sUmbv9/HlyxqnM2DzsvlBRml1UM8tro+Qpeh3+t/2FtzB0N9l1oR944DYjh7Z+VZkw6fhM/19P9T+ih1I983a4B/RjSbhM0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704250491; c=relaxed/simple; bh=CG3DrMhSoprVgveq4Cz30E7zQA0NX/LhLDfMUK3VezA=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=QY6Lk0T9S0nugJ06M44MUAHl3ZCUglN5kqYITTsP2yZjGIBiPB/HA+SaeEgt2W6JRDMFKOKO8YDWRM7b01pQua24dzy4hXD95JdvjqRNG7ehHKyFimLdyKaO83m9fpb9SjpDovt7+RxYi5GpcEPD5Z9YH93dYk9ytHERMhmy340= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-28be024282bso5072123a91.3 for ; Tue, 02 Jan 2024 18:54:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704250488; x=1704855288; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=xBl0gRIsH3L+6jSTb1QQIB0DdVNechcRY4vuw6h4ZFc=; b=StPRC3yTI9Uarj8xzxbWbKeqcscdTPafjHlrE7VWbkL8yn4u3wRxnU2krrbRj8d2Sl Jw0wX6DHR/qso+nU3TiKi/kYrvC6Iqo6VtHi4v/tprnQTQv/YxxcxiUBrqX8l+8shjav 8q32Z6BZFARAgPgPeWOrr3f87+H1rIckamwInIVvXcqCyggPYKTtvt6BvHKgBQb4XJJR skZF+14klQqCjEYAXk8H8IsSXGjWYj1lWrI0EiGICfZKRFCOP2mIw5xfavrooWHFAf1T Km52+7RfYYlgD328k1WezjNRMm9CE/3riO91vMusC5SJprMSoJl70lm0X4ZtQM9PcnU8 m54Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704250488; x=1704855288; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xBl0gRIsH3L+6jSTb1QQIB0DdVNechcRY4vuw6h4ZFc=; b=WK4RDrRwjRPfe7E2xYIcHEolMY3HBFcfGK+Jj1TswlJ3twQEeZs7n3cukhXUtbcU/4 CAubGoFZtkkG7v9nAiJUQZ4XUwHQ95amHeAhgntxmtUXpSIBTiZz2wmM9hfW5a1LesUe PfkGlrDvcgcqIiTEBYnERoHTjBZsfWdCJNZ2UWfBshvg5UYROlanPcA5JK48z5PzFz+N kNM7ez2VkS7Gx6oKKLKVSqQ1Ros7beHf2CmoZjcZWHMB+8Ztd7ovspwaLq81dnShmms+ o+fAhiNjvlyeUxSkoazZ7pAkJYDmxyZRVALUUwTgkjOadONk1hFMBJZl8dXBJbUPsYdX VRPw== X-Gm-Message-State: AOJu0YwzBn8utzNp2tjVDWF/+wepBB1aNB+Mms1U7pm5Y3zRzaGO1GQh 5bpkIHGIfvZ0KErRgG7k30inUfek85LrAFdeF5o= X-Google-Smtp-Source: AGHT+IGMmr9PSC/pOSDkWjeh56jtkrqkzdxJQ94B2LPG0rwWzsbvhnyFtJiEYYRyVj5rCg1h0f40pBpDOIm9YlnnHyo= X-Received: by 2002:a17:90a:744b:b0:28c:646b:b3ae with SMTP id o11-20020a17090a744b00b0028c646bb3aemr4631070pjk.7.1704250488291; Tue, 02 Jan 2024 18:54:48 -0800 (PST) MIME-Version: 1.0 References: <20231229040310.1047-1-cooper.joshua@linux.alibaba.com> <20231229041943.1366-1-cooper.joshua@linux.alibaba.com> <929ccf06-d106-40a5-b5b3-050d5aaf4875@gmail.com> In-Reply-To: From: Andrew Pinski Date: Tue, 2 Jan 2024 18:54:36 -0800 Message-ID: Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector. To: =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: Jeff Law , "cooper.joshua" , gcc-patches , "jim.wilson.gcc" , palmer , andrew , "philipp.tomsich" , =?UTF-8?Q?Christoph_M=C3=BCllner?= , jinma , Cooper Qu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-5.8 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Jan 1, 2024 at 2:59=E2=80=AFPM =E9=92=9F=E5=B1=85=E5=93=B2 wrote: > > This is Ok from my side. > But before commit this patch, I think we need this patch first: > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html > > I will be back to work so I will take a look at other patches today. Note I hate it. It would be better if you use something like `%^' (see `~` for an example of how that works) instead of hacking riscv_asm_output_opcode really. In fact that is how other targets implement this kind of things. Thanks, Andrew PInski > ________________________________ > juzhe.zhong@rivai.ai > > > From: Jeff Law > Date: 2024-01-01 01:43 > To: Jun Sha (Joshua); gcc-patches > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; = juzhe.zhong; Jin Ma; Xianmiao Qu > Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instruction= s of XTheadVector. > > > On 12/28/23 21:19, Jun Sha (Joshua) wrote: > > This patch adds th. prefix to all XTheadVector instructions by > > implementing new assembly output functions. We only check the > > prefix is 'v', so that no extra attribute is needed. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv-protos.h (riscv_asm_output_opcode): > > New function to add assembler insn code prefix/suffix. > > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise. > > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise. > > > > Co-authored-by: Jin Ma > > Co-authored-by: Xianmiao Qu > > Co-authored-by: Christoph M=C3=BCllner > > --- > > gcc/config/riscv/riscv-protos.h | 1 + > > gcc/config/riscv/riscv.cc | 14 +++++++++++++= + > > gcc/config/riscv/riscv.h | 4 ++++ > > .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 ++++++++++++ > > 4 files changed, 31 insertions(+) > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr= efix.c > > > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-p= rotos.h > > index 31049ef7523..5ea54b45703 100644 > > --- a/gcc/config/riscv/riscv-protos.h > > +++ b/gcc/config/riscv/riscv-protos.h > > @@ -102,6 +102,7 @@ struct riscv_address_info { > > }; > > > > /* Routines implemented in riscv.cc. */ > > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const = char *p); > > extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx= ); > > extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *)= ; > > extern int riscv_float_const_rtx_index_for_fli (rtx); > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > index 0d1cbc5cb5f..ea1d59d9cf2 100644 > > --- a/gcc/config/riscv/riscv.cc > > +++ b/gcc/config/riscv/riscv.cc > > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode) > > return lmul; > > } > > > > +/* Define ASM_OUTPUT_OPCODE to do anything special before > > + emitting an opcode. */ > > +const char * > > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p) > > +{ > > + /* We need to add th. prefix to all the xtheadvector > > + insturctions here.*/ > > + if (TARGET_XTHEADVECTOR && current_output_insn !=3D NULL_RTX && > > + p[0] =3D=3D 'v') > > + fputs ("th.", asm_out_file); > > + > > + return p; > Just a formatting nit. The GNU standards break lines before the > operator, not after. So > if (TARGET_XTHEADVECTOR > && current_output_insn !=3D NULL > && p[0] =3D=3D 'v') > > Note that current_output_insn is "extern rtx_insn *", so use NULL, not > NULL_RTX. > > Neither of these nits require a new version for review. Just fix them. > > If Juzhe is fine with this, so am I. We can refine it if necessary later= . > > jeff >