From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 6067 invoked by alias); 3 Feb 2015 06:05:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 6056 invoked by uid 89); 3 Feb 2015 06:05:33 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL,BAYES_50,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-la0-f49.google.com Received: from mail-la0-f49.google.com (HELO mail-la0-f49.google.com) (209.85.215.49) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 03 Feb 2015 06:05:31 +0000 Received: by mail-la0-f49.google.com with SMTP id gf13so48160371lab.8 for ; Mon, 02 Feb 2015 22:05:28 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.152.179.41 with SMTP id dd9mr21333514lac.66.1422943528543; Mon, 02 Feb 2015 22:05:28 -0800 (PST) Received: by 10.25.21.3 with HTTP; Mon, 2 Feb 2015 22:05:28 -0800 (PST) In-Reply-To: References: Date: Tue, 03 Feb 2015 06:05:00 -0000 Message-ID: Subject: Re: [PATCH, FT32] initial support From: Andrew Pinski To: James Bowman Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2015-02/txt/msg00108.txt.bz2 On Mon, Feb 2, 2015 at 9:18 PM, James Bowman wrote: > FT32 is a new high performance 32-bit RISC core developed by FTDI for embedded applications. > > Support for FT32 has already been added to binutils. This patch adds FT32 support to gcc. > > Please can someone review it, and if appropriate commit it, as I do not have write access to the tree. > > The FSF have acknowledged receipt of FTDI's copyright assignment papers. +(define_insn "umulsidi3" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (zero_extend:DI (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))) + ] + "" + "mul.l $cc,%1,%2\;muluh.l %h0,%1,%2\;move.l %0,$cc") Could you have a split of this instruction to allow better register allocation to happen? Also you are clobbering $cc but don't have a clobber for that register in the pattern. Likewise of: +(define_insn "abssi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (abs:SI (match_operand:SI 1 "register_operand" "r"))) + (clobber (match_scratch:SI 2 "=&r"))] + "" + "ashr.l\t%2,%1,31\;xor.l\t%0,%1,%2\;sub.l\t%0,%0,%2") You also have a few formatting issues dealing with if statements. An example: + /* If this is a store, force the value into a register. */ + if ( 1 && (! (reload_in_progress || reload_completed))) + { + if (MEM_P (operands[0])) + { it should be: if (!(reload_in_progress || reload_completed)) { if (MEM_P (operands[0])) { .... + " +{ + /* If this is a store, force the value into a register. */ + if (MEM_P (operands[0])) + operands[1] = force_reg (SFmode, operands[1]); + if (CONST_DOUBLE_P(operands[1])) + operands[1] = force_const_mem(SFmode, operands[1]); +}") You don't need the quotes around the {} in end of the patterns any more. An example: + " +{ + /* If this is a store, force the value into a register. */ + if (MEM_P (operands[0])) + operands[1] = force_reg (SFmode, operands[1]); + if (CONST_DOUBLE_P(operands[1])) + operands[1] = force_const_mem(SFmode, operands[1]); +}") You do some of the instructions have lengths but not all, the ones which matter the most are the ones where the output is more than one instruction. You implement some of the sync_* patterns instead of the newer atomic_* patterns. Thanks, Andrew Pinski > > Thanks very much. ChangeLog entry: > > 2014-02-03 James Bowman > > * configure.ac: FT32 target added > * libgcc/config.host: FT32 target added > * gcc/config/ft32/: FT32 target added > * libgcc/config/ft32/: FT32 target added > * configure: Regenerated > > -- > James Bowman > FTDI Open Source Liaison