From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4010 invoked by alias); 15 Nov 2012 21:39:09 -0000 Received: (qmail 4002 invoked by uid 22791); 15 Nov 2012 21:39:09 -0000 X-SWARE-Spam-Status: No, hits=-5.4 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,KHOP_RCVD_TRUST,KHOP_THREADED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE X-Spam-Check-By: sourceware.org Received: from mail-we0-f175.google.com (HELO mail-we0-f175.google.com) (74.125.82.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 15 Nov 2012 21:39:04 +0000 Received: by mail-we0-f175.google.com with SMTP id t44so798542wey.20 for ; Thu, 15 Nov 2012 13:39:03 -0800 (PST) MIME-Version: 1.0 Received: by 10.216.214.92 with SMTP id b70mr1221910wep.86.1353015543202; Thu, 15 Nov 2012 13:39:03 -0800 (PST) Received: by 10.217.64.194 with HTTP; Thu, 15 Nov 2012 13:39:03 -0800 (PST) In-Reply-To: References: <27d19005-b82d-4ecc-a81e-14208937ce0f@EXCHHUB01.MIPS.com> <1352921235.22862.6.camel@ubuntu-sellcey> <1352929552.22862.13.camel@ubuntu-sellcey> <87ip968twz.fsf@talisman.default> Date: Thu, 15 Nov 2012 21:39:00 -0000 Message-ID: Subject: Re: [patch] Performance patch for MIPS conditional move in expr.c From: Andrew Pinski To: Andrew Pinski , Steve Ellcey , gcc-patches@gcc.gnu.org, rdsandiford@googlemail.com Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2012-11/txt/msg01312.txt.bz2 On Thu, Nov 15, 2012 at 1:24 PM, Andrew Pinski wrote: > On Thu, Nov 15, 2012 at 12:58 PM, Richard Sandiford > wrote: >> Andrew Pinski writes: >>> 2012-07-26 Andrew Pinski >>> >>> Bug #3261 >>> * config/mips/mips.md (*mov_on_): >>> Remove mode check from comparisons. >>> (*mov_on_): Likewise. >>> (*mov_on__ne): New pattern to match >>> when (ne A 0) can be just A. >>> >>> * testsuite/gcc.target/mips/movcc-4.c: New testcase. >> >> OK, thanks (but remember to remove the internal bug reference :-)). >> I think this is early enough during stage 3 for the usual target >> flexibility to apply. > > I was posting it for Steve's benefit really. I was in the process of > updating the patch to the trunk and trying it out there before doing a > formal submission :). As I found out the testcase needs to be changed > to work with the new mips target test infrastructure. I will post a > revised patch with the removal of the internal bug number once I > finish fixing the testcase itself. After fixing up the testcase I find xori still in the resulting code: gcc$ ./cc1 t.c -O1 -o - -DNOMIPS16= -quiet -mabi=n32 -march=mips64 |grep xor xori $2,$4,0x1 But that is because combine produces: Trying 34 -> 35: Failed to match this instruction: (set (reg:SI 194 [ D.1393 ]) (if_then_else:SI (xor:SI (reg:SI 200 [ d ]) (const_int 1 [0x1])) (reg:SI 6 $6 [ c ]) (reg:SI 5 $5 [ b ]))) But does not switch around the if_then_else as reg 200 has a non zero bits of just 1. I will look into fix the rest of the problem later today. So the above patch is a way forward but not the full fix. Thanks, Andrew Pinski