From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 63977 invoked by alias); 27 Jun 2017 16:11:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 63875 invoked by uid 89); 27 Jun 2017 16:11:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=no version=3.3.2 spammy=meet X-HELO: mail-yw0-f176.google.com Received: from mail-yw0-f176.google.com (HELO mail-yw0-f176.google.com) (209.85.161.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 27 Jun 2017 16:11:28 +0000 Received: by mail-yw0-f176.google.com with SMTP id j11so13890573ywa.2 for ; Tue, 27 Jun 2017 09:11:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=Nu6w1dHN0mtQ0qBca67Mtp0R8wXGmPfi3J7geYOe1zQ=; b=JHi2yPXiTNCOtb6xMwIwfB8GuzjPB7IG8pj59hSS9nGzwB7fHSTXRKchYcyB3yehPy 1kUeCPpsIcxsqzWknZe5vPHdBurPWXO5DZSbx0GDaueGEylisWpnmWcfIGtF3pFNSLEZ JyDIenuhfM5DKBW38zAAeHqKhZJWFQDJHVqCLr0Z3JbPAytIAElfl0WV39UC2vJmbSdq W5VlX6eptEE5g3JsYoWFGh5Yh89NHwjVvhRjDgHgMO9cmulaF355+Yo/zGCpUOaoeH7V BowuF97huDOiBCvy8N4qbyDsLG+tvrc/a5D9Z2SoJuWoSSfJ+N2xG7+qRrKrb/QXWlX0 dbQg== X-Gm-Message-State: AKS2vOyNAlQuRHVOWYGoJ+hxVZbhYQx+PYifxjg+oErog9XAwpuQdrfw Q0O/2U4Sky2VV/232hNfL74VRuhQIQ== X-Received: by 10.129.67.4 with SMTP id q4mr4454182ywa.95.1498579885907; Tue, 27 Jun 2017 09:11:25 -0700 (PDT) MIME-Version: 1.0 Received: by 10.129.47.200 with HTTP; Tue, 27 Jun 2017 09:11:25 -0700 (PDT) In-Reply-To: <59527975.1060304@foss.arm.com> References: <59368A74.2060908@foss.arm.com> <59527975.1060304@foss.arm.com> From: Andrew Pinski Date: Tue, 27 Jun 2017 16:11:00 -0000 Message-ID: Subject: Re: [RFC][AARCH64]Add 'r' integer register operand modifier. Document the common asm modifier for aarch64 target. To: Renlin Li Cc: "gcc-patches@gcc.gnu.org" , James Greenhalgh , Ramana Radhakrishnan , Richard Earnshaw Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2017-06/txt/msg02069.txt.bz2 On Tue, Jun 27, 2017 at 8:27 AM, Renlin Li wrote: > Hi Andrew, > > On 25/06/17 22:38, Andrew Pinski wrote: >> >> On Tue, Jun 6, 2017 at 3:56 AM, Renlin Li wrote: >>> >>> Hi all, >>> >>> In this patch, a new integer register operand modifier 'r' is added. This >>> will use the >>> proper register name according to the mode of corresponding operand. >>> >>> 'w' register for scalar integer mode smaller than DImode >>> 'x' register for DImode >>> >>> This allows more flexibility and would meet people's expectations. >>> It will help for ILP32 and LP64, and big-endian case. >>> >>> A new section is added to document the AArch64 operand modifiers which >>> might >>> be used in inline assembly. It's not an exhaustive list covers every >>> modifier. >>> Only the most common and useful ones are documented. >>> >>> The default behavior of integer operand without modifier is clearly >>> documented >>> as well. It's not changed so that the patch shouldn't break anything. >>> >>> So with this patch, it should resolve the issues in PR63359. >>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63359 >>> >>> >>> aarch64-none-elf regression test Okay. Okay to check in? >> >> >> I think 'r' modifier is very fragile and can be used incorrectly and >> wrong in some cases really.. > > > The user could always (or be encouraged to) opt to a strict register > modifier to enforce consistent behavior in all cases. > > I agree the flexibility might bring unexpected behavior in corner cases. > Do you have any examples to share off the top of your head? So that we can > discuss the benefit and pitfalls, and decide to improve the patch or > withdraw it. One thing is TImode is missing. I have an use case of __int128_t inside inline-asm. For me %r and TImode would produce "x0, x1". This is one of the reasons why I said it is fragile. > >> I like the documentation though. As an aside %H is not documented here. Noticed it because I am using %H with TImode. Thanks, Andrew > > Thanks, > Renlin > > >> >> Thanks, >> Andrew >> >>> >>> gcc/ChangeLog: >>> >>> 2017-06-06 Renlin Li >>> >>> PR target/63359 >>> * config/aarch64/aarch64.c (aarch64_print_operand): Add 'r' >>> modifier. >>> * doc/extend.texi (AArch64Operandmodifiers): New section.