From: Andrew Pinski <pinskia@gmail.com>
To: Jiong Wang <jiong.wang@arm.com>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>
Subject: Re: [AArch64] Improve TLS Descriptor pattern to release RTL loop IV opt
Date: Sat, 26 Sep 2015 07:42:00 -0000 [thread overview]
Message-ID: <CA+=Sn1nBYTJuJwz5iZQuJjRx-DLq+Um3qUF0461UT=doNbXv5g@mail.gmail.com> (raw)
In-Reply-To: <CA+=Sn1=3iHvxECyM7qc6zKrXB_uccnyV2-q8y1m4Jt4zkKKsbg@mail.gmail.com>
On Fri, Sep 25, 2015 at 11:40 PM, Andrew Pinski <pinskia@gmail.com> wrote:
> On Tue, Jul 28, 2015 at 6:12 AM, Jiong Wang <jiong.wang@arm.com> wrote:
>>
>> The instruction sequences for preparing argument for TLS descriptor
>> runtime resolver and the later function call to resolver can actually be
>> hoisted out of the loop.
>>
>> Currently we can't because we have exposed the hard register X0 as
>> destination of "set". While GCC's RTL data flow infrastructure will
>> skip or do very conservative assumption when hard register involved in
>> and thus some loop IV opportunities are missed.
>>
>> This patch add another "tlsdesc_small_pseudo_<mode>" pattern, and avoid
>> expose x0 to gcc generic code.
>>
>> Generally, we define a new register class FIXED_R0 which only contains register
>> 0, so the instruction sequences generated from the new add pattern is the same
>> as tlsdesc_small_<mode>, while the operand 0 is wrapped as pseudo register that
>> RTL IV opt can handle it.
>>
>> Ideally, we should allow operand 0 to be any pseudo register, but then
>> we can't model the override of x0 caused by the function call which is
>> hidded by the UNSPEC.
>>
>> So here, we restricting operand 0 to be x0, the override of x0 can be
>> reflected to the gcc.
>>
>> OK for trunk?
>
>
> This patch broke ILP32 because we used mode rather than ptr_mode for
> the psedu . I have an idea on how to fix it (like tlsie_small_sidi
> case) but I still need to test it fully.
>
> This is the smallest testcase where the problem is:
> struct dtor_list
> {
> struct dtor_list *next;
> };
> static __thread struct dtor_list *tls_dtor_list;
> __cxa_thread_atexit_impl ( struct dtor_list *new)
> {
> new->next = tls_dtor_list;
> tls_dtor_list = new;
> }
Actually there is another bug with respect of the output too. Some of
the <w>0 should have been plain x0 due to only the 64bit register is
accepted in some contexts.
Thanks,
Andrew
>
>
> Thanks,
> Andrew
>
>>
>> 2015-07-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
>> Jiong Wang <jiong.wang@arm.com>
>>
>> gcc/
>> * config/aarch64/aarch64.d (tlsdesc_small_pseudo_<mode>): New pattern.
>> * config/aarch64/aarch64.h (reg_class): New enumeration FIXED_REG0.
>> (REG_CLASS_NAMES): Likewise.
>> (REG_CLASS_CONTENTS): Likewise.
>> * config/aarch64/aarch64.c (aarch64_class_max_nregs): Likewise.
>> (aarch64_register_move_cost): Likewise.
>> (aarch64_load_symref_appropriately): Invoke the new added pattern if
>> possible.
>> * config/aarch64/constraints.md (Uc0): New constraint.
>>
>> gcc/testsuite.
>> * gcc.target/aarch64/tlsdesc_hoist.c: New testcase.
>>
>> --
>> Regards,
>> Jiong
>>
next prev parent reply other threads:[~2015-09-26 6:48 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-28 14:02 Jiong Wang
2015-08-04 9:48 ` James Greenhalgh
2015-08-06 16:13 ` [COMMITTED][AArch64] " Jiong Wang
2015-08-08 11:59 ` Andreas Schwab
2015-08-10 10:28 ` Jiong Wang
2015-08-10 13:08 ` Jiong Wang
2015-08-10 13:20 ` Andreas Schwab
2015-08-10 13:26 ` Jiong Wang
2015-08-10 13:33 ` Andreas Schwab
2015-08-10 22:55 ` Jiong Wang
2015-08-11 7:11 ` Andreas Schwab
2015-08-11 8:36 ` Jiong Wang
2015-08-11 8:48 ` Jiong Wang
2015-08-11 11:22 ` [COMMITTED][AArch64] Add the missing "," for enumeration element Jiong Wang
2015-09-26 7:38 ` [AArch64] Improve TLS Descriptor pattern to release RTL loop IV opt Andrew Pinski
2015-09-26 7:42 ` Andrew Pinski [this message]
2015-09-28 15:17 ` Jiong Wang
2015-09-28 17:08 ` Jiong Wang
2015-09-28 16:10 ` Marcus Shawcroft
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