From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 46887 invoked by alias); 26 Sep 2015 06:48:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 46875 invoked by uid 89); 26 Sep 2015 06:48:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-la0-f50.google.com Received: from mail-la0-f50.google.com (HELO mail-la0-f50.google.com) (209.85.215.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Sat, 26 Sep 2015 06:48:31 +0000 Received: by lacrr8 with SMTP id rr8so38987560lac.2 for ; Fri, 25 Sep 2015 23:48:27 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.112.52.168 with SMTP id u8mr2731606lbo.48.1443250107424; Fri, 25 Sep 2015 23:48:27 -0700 (PDT) Received: by 10.25.160.73 with HTTP; Fri, 25 Sep 2015 23:48:27 -0700 (PDT) In-Reply-To: References: Date: Sat, 26 Sep 2015 07:42:00 -0000 Message-ID: Subject: Re: [AArch64] Improve TLS Descriptor pattern to release RTL loop IV opt From: Andrew Pinski To: Jiong Wang Cc: gcc-patches Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2015-09/txt/msg02043.txt.bz2 On Fri, Sep 25, 2015 at 11:40 PM, Andrew Pinski wrote: > On Tue, Jul 28, 2015 at 6:12 AM, Jiong Wang wrote: >> >> The instruction sequences for preparing argument for TLS descriptor >> runtime resolver and the later function call to resolver can actually be >> hoisted out of the loop. >> >> Currently we can't because we have exposed the hard register X0 as >> destination of "set". While GCC's RTL data flow infrastructure will >> skip or do very conservative assumption when hard register involved in >> and thus some loop IV opportunities are missed. >> >> This patch add another "tlsdesc_small_pseudo_" pattern, and avoid >> expose x0 to gcc generic code. >> >> Generally, we define a new register class FIXED_R0 which only contains register >> 0, so the instruction sequences generated from the new add pattern is the same >> as tlsdesc_small_, while the operand 0 is wrapped as pseudo register that >> RTL IV opt can handle it. >> >> Ideally, we should allow operand 0 to be any pseudo register, but then >> we can't model the override of x0 caused by the function call which is >> hidded by the UNSPEC. >> >> So here, we restricting operand 0 to be x0, the override of x0 can be >> reflected to the gcc. >> >> OK for trunk? > > > This patch broke ILP32 because we used mode rather than ptr_mode for > the psedu . I have an idea on how to fix it (like tlsie_small_sidi > case) but I still need to test it fully. > > This is the smallest testcase where the problem is: > struct dtor_list > { > struct dtor_list *next; > }; > static __thread struct dtor_list *tls_dtor_list; > __cxa_thread_atexit_impl ( struct dtor_list *new) > { > new->next = tls_dtor_list; > tls_dtor_list = new; > } Actually there is another bug with respect of the output too. Some of the 0 should have been plain x0 due to only the 64bit register is accepted in some contexts. Thanks, Andrew > > > Thanks, > Andrew > >> >> 2015-07-28 Ramana Radhakrishnan >> Jiong Wang >> >> gcc/ >> * config/aarch64/aarch64.d (tlsdesc_small_pseudo_): New pattern. >> * config/aarch64/aarch64.h (reg_class): New enumeration FIXED_REG0. >> (REG_CLASS_NAMES): Likewise. >> (REG_CLASS_CONTENTS): Likewise. >> * config/aarch64/aarch64.c (aarch64_class_max_nregs): Likewise. >> (aarch64_register_move_cost): Likewise. >> (aarch64_load_symref_appropriately): Invoke the new added pattern if >> possible. >> * config/aarch64/constraints.md (Uc0): New constraint. >> >> gcc/testsuite. >> * gcc.target/aarch64/tlsdesc_hoist.c: New testcase. >> >> -- >> Regards, >> Jiong >>