From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7013 invoked by alias); 4 Feb 2015 16:49:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 7001 invoked by uid 89); 4 Feb 2015 16:49:54 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lb0-f173.google.com Received: from mail-lb0-f173.google.com (HELO mail-lb0-f173.google.com) (209.85.217.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Wed, 04 Feb 2015 16:49:53 +0000 Received: by mail-lb0-f173.google.com with SMTP id p9so2558604lbv.4 for ; Wed, 04 Feb 2015 08:49:50 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.152.179.41 with SMTP id dd9mr30100500lac.66.1423068590122; Wed, 04 Feb 2015 08:49:50 -0800 (PST) Received: by 10.25.21.3 with HTTP; Wed, 4 Feb 2015 08:49:50 -0800 (PST) In-Reply-To: <6D39441BF12EF246A7ABCE6654B0235320FC7F04@LEMAIL01.le.imgtec.org> References: <6D39441BF12EF246A7ABCE6654B0235320FC7F04@LEMAIL01.le.imgtec.org> Date: Wed, 04 Feb 2015 16:49:00 -0000 Message-ID: Subject: Re: [PATCH,WWWDOCS] MIPS changes for GCC 5.0 From: Andrew Pinski To: Matthew Fortune Cc: "Moore, Catherine (Catherine_Moore@mentor.com)" , "'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)" Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2015-02/txt/msg00261.txt.bz2 On Wed, Feb 4, 2015 at 8:46 AM, Matthew Fortune wrote: > Hi Catherine, > > I've made a first pass at writing up the MIPS changes for GCC 5.0. > Could you take a read and see what needs some more work? One comment below. > > Thanks, > Matthew > > Index: htdocs/gcc-5/changes.html > =================================================================== > RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-5/changes.html,v > retrieving revision 1.77 > diff -r1.77 changes.html > 562a563,614 >>

MIPS

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    >>
  • MIPS Releases 3 and 5 are now directly supported using -mips32r3, >> -mips64r3, -mips32r5 and -mips64r5 instead of relying on the Release >> 2 options.
    • >>
  • Support for the Imagination P5600 processor has been added using >> -march=p5600. >>
    • >>
  • Support for the Cavium Networks Octeon3 processor has been added using >> -march=octeon3.
    • We are known as just Cavium now. That is remove the Networks part. Thanks, Andrew >>
  • MIPS Release 6 is now supported using -mips32r6 and -mips64r6 >> . >>
  • The previous o32 64-bit floating-point register support has been >> obsoleted and removed. This was previously enabled using -mfp64 >> which has been re-purposed for the new ABI extensions described >> below.
    • >>
  • New o32 ABI extensions have been added to enable software to transition >> away from the original layout of double-precision floating-point registers. >>
      >>
    • The first of these extensions is o32 FPXX which places restrictions >> on code-generation to never access the upper 32-bits of double-precision >> registers via odd-numbered single-precision registers. By default the >> odd-numbered single-precision registers are not used at all with this >> extension. o32 FPXX code is link compatible with all other o32 >> double-precision ABI variants and will execute correctly in all hardware >> FPU modes. Enable o32 FPXX using -mabi=32 -mfpxx for >> MIPS II onwards.
      • >>
    • The second extension is o32 FP64A which requires 64-bit >> floating-point registers and places a mandatory restriction on the use of >> odd-numbered single-precision registers. o32 FP64A is link compatible >> with all other o32 double-precision ABI variants. Enable o32 FP64A >> using -mabi=32 -mfp64 -mno-odd-spreg for MIPS32R2 onwards. >>
      • >>
    • Finally, the o32 FP64 extension which also requires 64-bit >> floating-point registers but permits the use of all single-precision >> registers. Enable o32 FP64 using -mfp64 for MIPS32R2 >> onwards.
      • >>
    >> All new ABI variants can be enabled by default using configure time >> options --with-fp-32=[32|xx|64] and >> --with(out)-odd-sp-reg-32. It is strongly recommended that >> all vendors begin to set o32 FPXX as default ABI to be able to run the >> generated code on MIPSR5 cores alongside future MIPS SIMD (MSA) code and >> MIPSR6 cores.
    • >>
  • When using binutils 2.25 GCC will now pass options like >> -msoft-float and -msingle-float to the assembler. >> This change can affect inline assembly code that is built as soft-float but >> contains hard-float instructions. In such cases the code must be amended >> to use appropriate .set directives to override the global >> assembler options.
    • >>
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