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Date: Tue, 20 Oct 2015 00:33:00 -0000
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Subject: Re: [PATCH][AArch64] Replace insn to zero up DF register
From: Andrew Pinski <pinskia@gmail.com>
To: Evandro Menezes <e.menezes@samsung.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>, Marcus Shawcroft <Marcus.Shawcroft@arm.com>, 	Kyrill Tkachov <kyrylo.tkachov@arm.com>
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On Tue, Oct 20, 2015 at 7:51 AM, Andrew Pinski <pinskia@gmail.com> wrote:
> On Tue, Oct 20, 2015 at 7:40 AM, Evandro Menezes <e.menezes@samsung.com> wrote:
>> In the existing targets, it seems that it's always faster to zero up a DF
>> register with "movi %d0, #0" instead of "fmov %d0, xzr".
>
> I think for ThunderX 1, this change will not make a difference.  So I
> am neutral on this change.

Actually depending on fmov is decoded in our pipeline, this change
might actually be worse.  Currently fmov with an immediate is 1 cycle
while movi is two cycles.  Let me double check how internally on how
it is decoded and if it is 1 cycle or two.

Thanks,
Andrew

>
> Thanks,
> Andrew
>
>>
>> This patch modifies the respective pattern.
>>
>> Please, commit if it's alright.
>>
>> Thank you,
>>
>> --
>> Evandro Menezes
>>