* [PATCH] AARCH64: Add Qualcomnm oryon-1 core @ 2024-05-03 19:49 Andrew Pinski 2024-05-14 17:26 ` Kyrill Tkachov 0 siblings, 1 reply; 3+ messages in thread From: Andrew Pinski @ 2024-05-03 19:49 UTC (permalink / raw) To: gcc-patches; +Cc: Andrew Pinski, Joel Jones, Wei Zhao This patch adds Qualcomm's new oryon-1 core; this is enough to recongize the core and later on will add the tuning structure. gcc/ChangeLog: * config/aarch64/aarch64-cores.def (oryon-1): New entry. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi (AArch64 Options): Document oryon-1. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com> Co-authored-by: Joel Jones <quic_joeljone@quicinc.com> Co-authored-by: Wei Zhao <quic_wezhao@quicinc.com> --- gcc/config/aarch64/aarch64-cores.def | 5 +++++ gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/doc/invoke.texi | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index f69fc212d56..be60929e400 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -151,6 +151,11 @@ AARCH64_CORE("neoverse-512tvb", neoverse512tvb, cortexa57, V8_4A, (SVE, I8MM, B /* Qualcomm ('Q') cores. */ AARCH64_CORE("saphira", saphira, saphira, V8_4A, (CRYPTO), saphira, 0x51, 0xC01, -1) +/* ARMv8.6-A Architecture Processors. */ + +/* Qualcomm ('Q') cores. */ +AARCH64_CORE("oryon-1", oryon1, cortexa57, V8_6A, (CRYPTO, SM4, SHA3, F16), cortexa72, 0x51, 0x001, -1) + /* ARMv8-A big.LITTLE implementations. */ AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, V8A, (CRC), cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1) diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index abd3c9e0822..ba940f1c890 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,ampere1b,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neoversen2,cobalt100,neoversev2,demeter,generic,generic_armv8_a,generic_armv9_a" + "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,ampere1b,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,saphira,oryon1,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neoversen2,cobalt100,neoversev2,demeter,generic,generic_armv8_a,generic_armv9_a" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9456ced468a..eabe09dc28f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21323,6 +21323,7 @@ performance of the code. Permissible values for this option are: @samp{cortex-a65}, @samp{cortex-a65ae}, @samp{cortex-a34}, @samp{cortex-a78}, @samp{cortex-a78ae}, @samp{cortex-a78c}, @samp{ares}, @samp{exynos-m1}, @samp{emag}, @samp{falkor}, +@samp{oyron-1}, @samp{neoverse-512tvb}, @samp{neoverse-e1}, @samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{neoverse-v2}, @samp{qdf24xx}, @samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan}, -- 2.43.0 ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] AARCH64: Add Qualcomnm oryon-1 core 2024-05-03 19:49 [PATCH] AARCH64: Add Qualcomnm oryon-1 core Andrew Pinski @ 2024-05-14 17:26 ` Kyrill Tkachov 2024-05-23 3:50 ` Andrew Pinski 0 siblings, 1 reply; 3+ messages in thread From: Kyrill Tkachov @ 2024-05-14 17:26 UTC (permalink / raw) To: Andrew Pinski; +Cc: gcc-patches, Joel Jones, Wei Zhao [-- Attachment #1: Type: text/plain, Size: 4639 bytes --] Hi Andrew, On Fri, May 3, 2024 at 8:50 PM Andrew Pinski <quic_apinski@quicinc.com> wrote: > This patch adds Qualcomm's new oryon-1 core; this is enough > to recongize the core and later on will add the tuning structure. > > gcc/ChangeLog: > > * config/aarch64/aarch64-cores.def (oryon-1): New entry. > * config/aarch64/aarch64-tune.md: Regenerate. > * doc/invoke.texi (AArch64 Options): Document oryon-1. > > Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com> > Co-authored-by: Joel Jones <quic_joeljone@quicinc.com> > Co-authored-by: Wei Zhao <quic_wezhao@quicinc.com> > --- > gcc/config/aarch64/aarch64-cores.def | 5 +++++ > gcc/config/aarch64/aarch64-tune.md | 2 +- > gcc/doc/invoke.texi | 1 + > 3 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/gcc/config/aarch64/aarch64-cores.def > b/gcc/config/aarch64/aarch64-cores.def > index f69fc212d56..be60929e400 100644 > --- a/gcc/config/aarch64/aarch64-cores.def > +++ b/gcc/config/aarch64/aarch64-cores.def > @@ -151,6 +151,11 @@ AARCH64_CORE("neoverse-512tvb", neoverse512tvb, > cortexa57, V8_4A, (SVE, I8MM, B > /* Qualcomm ('Q') cores. */ > AARCH64_CORE("saphira", saphira, saphira, V8_4A, (CRYPTO), > saphira, 0x51, 0xC01, -1) > > +/* ARMv8.6-A Architecture Processors. */ > + > +/* Qualcomm ('Q') cores. */ > +AARCH64_CORE("oryon-1", oryon1, cortexa57, V8_6A, (CRYPTO, SM4, SHA3, > F16), cortexa72, 0x51, 0x001, -1) > + > /* ARMv8-A big.LITTLE implementations. */ > > AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, > V8A, (CRC), cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1) > diff --git a/gcc/config/aarch64/aarch64-tune.md > b/gcc/config/aarch64/aarch64-tune.md > index abd3c9e0822..ba940f1c890 100644 > --- a/gcc/config/aarch64/aarch64-tune.md > +++ b/gcc/config/aarch64/aarch64-tune.md > @@ -1,5 +1,5 @@ > ;; -*- buffer-read-only: t -*- > ;; Generated automatically by gentune.sh from aarch64-cores.def > (define_attr "tune" > - > "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,ampere1b,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neoversen2,cobalt100,neoversev2,demeter,generic,generic_armv8_a,generic_armv9_a" > + > "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,ampere1b,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,saphira,oryon1,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neoversen2,cobalt100,neoversev2,demeter,generic,generic_armv8_a,generic_armv9_a" > (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 9456ced468a..eabe09dc28f 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -21323,6 +21323,7 @@ performance of the code. Permissible values for > this option are: > @samp{cortex-a65}, @samp{cortex-a65ae}, @samp{cortex-a34}, > @samp{cortex-a78}, @samp{cortex-a78ae}, @samp{cortex-a78c}, > @samp{ares}, @samp{exynos-m1}, @samp{emag}, @samp{falkor}, > +@samp{oyron-1}, Typo in the name. LGTM with that fixed. Thanks, Kyrill > > @samp{neoverse-512tvb}, @samp{neoverse-e1}, @samp{neoverse-n1}, > @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{neoverse-v2}, > @samp{qdf24xx}, > @samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan}, > -- > 2.43.0 > > ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] AARCH64: Add Qualcomnm oryon-1 core 2024-05-14 17:26 ` Kyrill Tkachov @ 2024-05-23 3:50 ` Andrew Pinski 0 siblings, 0 replies; 3+ messages in thread From: Andrew Pinski @ 2024-05-23 3:50 UTC (permalink / raw) To: Kyrill Tkachov; +Cc: Andrew Pinski, gcc-patches, Joel Jones, Wei Zhao On Tue, May 14, 2024 at 10:27 AM Kyrill Tkachov <kyrilltkachov33@googlemail.com> wrote: > > Hi Andrew, > > On Fri, May 3, 2024 at 8:50 PM Andrew Pinski <quic_apinski@quicinc.com> wrote: >> >> This patch adds Qualcomm's new oryon-1 core; this is enough >> to recongize the core and later on will add the tuning structure. >> >> gcc/ChangeLog: >> >> * config/aarch64/aarch64-cores.def (oryon-1): New entry. >> * config/aarch64/aarch64-tune.md: Regenerate. >> * doc/invoke.texi (AArch64 Options): Document oryon-1. >> >> Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com> >> Co-authored-by: Joel Jones <quic_joeljone@quicinc.com> >> Co-authored-by: Wei Zhao <quic_wezhao@quicinc.com> >> --- >> gcc/config/aarch64/aarch64-cores.def | 5 +++++ >> gcc/config/aarch64/aarch64-tune.md | 2 +- >> gcc/doc/invoke.texi | 1 + >> 3 files changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def >> index f69fc212d56..be60929e400 100644 >> --- a/gcc/config/aarch64/aarch64-cores.def >> +++ b/gcc/config/aarch64/aarch64-cores.def >> @@ -151,6 +151,11 @@ AARCH64_CORE("neoverse-512tvb", neoverse512tvb, cortexa57, V8_4A, (SVE, I8MM, B >> /* Qualcomm ('Q') cores. */ >> AARCH64_CORE("saphira", saphira, saphira, V8_4A, (CRYPTO), saphira, 0x51, 0xC01, -1) >> >> +/* ARMv8.6-A Architecture Processors. */ >> + >> +/* Qualcomm ('Q') cores. */ >> +AARCH64_CORE("oryon-1", oryon1, cortexa57, V8_6A, (CRYPTO, SM4, SHA3, F16), cortexa72, 0x51, 0x001, -1) >> + >> /* ARMv8-A big.LITTLE implementations. */ >> >> AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, V8A, (CRC), cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1) >> diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md >> index abd3c9e0822..ba940f1c890 100644 >> --- a/gcc/config/aarch64/aarch64-tune.md >> +++ b/gcc/config/aarch64/aarch64-tune.md >> @@ -1,5 +1,5 @@ >> ;; -*- buffer-read-only: t -*- >> ;; Generated automatically by gentune.sh from aarch64-cores.def >> (define_attr "tune" >> - "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,ampere1b,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neoversen2,cobalt100,neoversev2,demeter,generic,generic_armv8_a,generic_armv9_a" >> + "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,ampere1b,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,saphira,oryon1,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neoversen2,cobalt100,neoversev2,demeter,generic,generic_armv8_a,generic_armv9_a" >> (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) >> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi >> index 9456ced468a..eabe09dc28f 100644 >> --- a/gcc/doc/invoke.texi >> +++ b/gcc/doc/invoke.texi >> @@ -21323,6 +21323,7 @@ performance of the code. Permissible values for this option are: >> @samp{cortex-a65}, @samp{cortex-a65ae}, @samp{cortex-a34}, >> @samp{cortex-a78}, @samp{cortex-a78ae}, @samp{cortex-a78c}, >> @samp{ares}, @samp{exynos-m1}, @samp{emag}, @samp{falkor}, >> +@samp{oyron-1}, > > > Typo in the name. > LGTM with that fixed. Thanks, pushed as r15-784-g01cfd601825014. Thanks, Andrew > Thanks, > Kyrill > >> >> >> @samp{neoverse-512tvb}, @samp{neoverse-e1}, @samp{neoverse-n1}, >> @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{neoverse-v2}, @samp{qdf24xx}, >> @samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan}, >> -- >> 2.43.0 >> ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2024-05-23 3:50 UTC | newest] Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2024-05-03 19:49 [PATCH] AARCH64: Add Qualcomnm oryon-1 core Andrew Pinski 2024-05-14 17:26 ` Kyrill Tkachov 2024-05-23 3:50 ` Andrew Pinski
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).