From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by sourceware.org (Postfix) with ESMTPS id 3B033385ED4B for ; Tue, 4 Aug 2020 15:40:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 3B033385ED4B Received: by mail-wm1-x344.google.com with SMTP id 3so3385706wmi.1 for ; Tue, 04 Aug 2020 08:40:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Vl+pfHFbSmmshCQIGJlr1EGrpr6a5AaBO4uGp89s5XA=; b=tZtHnUa5ur5ENBWDUvp5NZPhmy+1VQjhaN2aERV+vW2kgSyTFtR9PqCOLIMGyzqyF7 W8XajWOgixLD2uBiGXRP5tVd7mT9yOoUiPTg4KkfDgZ2ExcAv7jfq7hs7SHvl+8c9Jno LG2twRo9gmxjLR32s4eE15qM8dLqvm+KlJ9KQuQEfJ3jDNVmJL+grN7d7xPuELYifsuT O1F6MRNokBov5CoOgf+mPP9SFDYR01lXrxS+1Q6aG9TbS5Yr1jypJi5JcujJBnJt9paM TAoZpM7Mm0IFSgWGo6LQVnmd3HoFtTnoFUYn9ROHp0Mlcq5SGmeRBCijZJHMZeHpYRBI 1mzQ== X-Gm-Message-State: AOAM533qhIaUa5WrP+b630uBAhrc71fWsMNBIwc3Ghn0to/gbvt0ADft PgihTB3m50Kadg6mVARIWx7ZaMM9cZ7aYD3VgAI= X-Google-Smtp-Source: ABdhPJwkouy6I6rBqct1tPL6DWCZCmFzeEKvBaIeKTu29KYfyzj2GTHyfrEG8YOEqCT5/uKLt0o4TnSbayzjSlsRp+g= X-Received: by 2002:a1c:66c5:: with SMTP id a188mr4479355wmc.173.1596555625305; Tue, 04 Aug 2020 08:40:25 -0700 (PDT) MIME-Version: 1.0 References: <20200804144710.bfpkz342chp7ql65@kyukhin> In-Reply-To: <20200804144710.bfpkz342chp7ql65@kyukhin> From: Hongyu Wang Date: Tue, 4 Aug 2020 23:40:14 +0800 Message-ID: Subject: Re: [PATCH] Enable GCC support for AMX To: Kirill Yukhin Cc: gcc-patches@gcc.gnu.org, ubizjak@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=0.4 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Aug 2020 15:40:27 -0000 Kirill Yukhin =E4=BA=8E2020=E5=B9=B48=E6=9C=884= =E6=97=A5=E5=91=A8=E4=BA=8C =E4=B8=8B=E5=8D=8810:47=E5=86=99=E9=81=93=EF=BC= =9A > > Hello, > > On 06 =D0=B8=D1=8E=D0=BB 09:58, Hongyu Wang via Gcc-patches wrote: > > Hi: > > > > This patch is about to support Intel Advanced Matrix Extensions (AMX) > > which will be enabled in GLC. > > > > AMX is a new 64-bit programming paradigm consisting of two > > compo nents: a set of 2-dimensional registers (tiles) representing > > sub-arrays from a larger 2-dimensional memory image, > > and an accelerator able to operate on tiles > > > > Supported instructions are > > > > AMX-TILE:ldtilecfg/sttilecfg/tileloadd/tileloaddt1/tilezero/tilerelease > > AMX-INT8:tdpbssd/tdpbsud/tdpbusd/tdpbuud > > AMX-BF16:tdpbf16ps > > > > The intrinsics adopts constant tile register number as its input parame= ters. > > I didn't go into the patch deeply, but why did you use inline asm for int= rinsics > definition? Are you going to introduce register classes for thouse new tm= m > registers and new instruction definitions for new insns in machine descri= ption? In this version of patch, we just align our implementation to what have been submitted to llvm community. Since AMX allows variant register size in runtime configuration, the implementation of register allocation is still under discussion. We will introduce new register class and new insns in the future patch. > > -- > K