* Enable GCC support for Intel Key Locker extension
@ 2020-09-21 5:30 Hongyu Wang
0 siblings, 0 replies; only message in thread
From: Hongyu Wang @ 2020-09-21 5:30 UTC (permalink / raw)
To: GCC Patches, Kirill Yukhin
[-- Attachment #1: Type: text/plain, Size: 5743 bytes --]
Hi:
This patch is about to support Intel Key Locker extension.
Key Locker provides a mechanism to encrypt and decrypt data with an AES key
without having access to the raw key value.
For more details, please refer to
https://software.intel.com/content/dam/develop/external/us/en/documents/343965-intel-key-locker-specification.pdf
.
Bootstrap ok, regression test on i386/x86 backend is ok.
OK for master?
gcc/ChangeLog
* common/config/i386/cpuinfo.h (get_available_features):
Detect KL, AESKLE and WIDEKL features.
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_KL_SET): New.
(OPTION_MASK_ISA_WIDEKL_SET): Likewise.
(OPTION_MASK_ISA_KL_UNSET): Likewise.
(OPTION_MASK_ISA_WIDEKL_UNSET): Likewise.
(OPTION_MASK_ISA2_AVX2_UNSET): Likewise.
(OPTION_MASK_ISA2_AVX_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE4_2_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE4_1_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE4_UNSET): Likewise.
(OPTION_MASK_ISA2_SSSE3_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE3_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE2_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE_UNSET): Likewise.
(ix86_handle_option): Handle kl and widekl, add dependency chain
for KL and SSE2.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
(FEATURE_KL, FEATURE_AESKLE, FEATURE_WIDEKL): New.
* common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY
for KL, AESKLE and WIDEKL.
* config.gcc: Add keylockerintrin.h.
* doc/invoke.texi: Document new option -mkl and -mwidekl.
* doc/extend.texi: Document kl and widekl.
* config/i386/constraints.md
(Y1, Y2, Y3, Y4, Y5, Y6, Y7): New register constraints.
* config/i386/cpuid.h (bit_KL, bit_AESKLE, bit_WIDEKL): New.
* config/i386/i386-builtin-types.def ((UINT, UINT, V2DI, V2DI,
PVOID),
(UINT, UINT, V2DI, PVOID), (VOID, V2DI, V2DI, V2DI, UINT),
(UINT8, PV2DI, V2DI, PCVOID), (UINT8, PV2DI, PCV2DI, PCVOID)):
New
function types.
* config/i386/i386-builtin.def: Add
__builtin_ia32_loadiwkey,
__builtin_ia32_aesdec128kl_u8,
__builtin_ia32_aesdec256kl_u8,
__builtin_ia32_aesenc128kl_u8,
__builtin_ia32_aesenc256kl_u8,
__builtin_ia32_aesdecwide128kl_u8,
__builtin_ia32_aesdecwide256kl_u8,
__builtin_ia32_aesencwide128kl_u8,
__builtin_ia32_aesencwide256kl_u8,
__builtin_ia32_encodekey128_u32,
__builtin_ia32_encodekey256_u32.
* config/i386/i386-c.c (ix86_target_macros_internal): Handle
kl and widekl.
* config/i386/i386-options.c (isa2_opts): Add -mkl and -mwidekl.
(ix86_option_override_internal): Handle KL and WIDEKL.
(ix86_valid_target_attribute_inner_p): Add attribute for kl and
widekl.
* config/i386/i386-expand.c
(ix86_expand_builtin): Expand Keylocker Builtins.
* config/i386/i386.h (TARGET_KL): New.
(TARGET_KL_P): Likewise.
(TARGET_WIDEKL): Likewise.
(TARGET_WIDEKL_P): Likewise.
(PTA_KL): Likewise.
(PTA_WIDEKL): Likewise.
(enum reg_class): Add 7 new SSE register classes.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
* config/i386/i386.opt: Add new option mkl and mwidekl.
* config/i386/keylockerintrin.h: New header file for Keylocker.
* config/i386/immintrin.h: Include keylockerintrin.h.
* config/i386/sse.md (UNSPECV_LOADIWKEY): New.
(UNSPECV_AESDEC128KLU8): Likewise.
(UNSPECV_AESENC128KLU8): Likewise.
(UNSPECV_AESDEC256KLU8): Likewise.
(UNSPECV_AESENC256KLU8): Likewise.
(UNSPECV_AESDECWIDE128KLU8): Likewise.
(UNSPECV_AESENCWIDE128KLU8): Likewise.
(UNSPECV_AESDECWIDE256KLU8): Likewise.
(UNSPECV_AESENCWIDE256KLU8): Likewise.
(UNSPECV_ENCODEKEY128U32): Likewise.
(UNSPECV_ENCODEKEY256U32): Likewise.
(loadiwkey): New insn pattern.
(encodekey128u32): Likewise.
(encodekey256u32): Likewise.
(aes<aesklvariant>u8): Likewise.
(aes<aeswideklvariant>u8): Likewise.
gcc/testsuite/ChangeLog
* gcc.target/i386/keylocker-aesdec128kl.c: New test.
* gcc.target/i386/keylocker-aesdec256kl.c: Likewise.
* gcc.target/i386/keylocker-aesdecwide128kl.c: Likewise.
* gcc.target/i386/keylocker-aesdecwide256kl.c: Likewise.
* gcc.target/i386/keylocker-aesenc128kl.c: Likewise.
* gcc.target/i386/keylocker-aesencwide128kl.c: Likewise.
* gcc.target/i386/keylocker-aesencwide256kl.c: Likewise.
* gcc.target/i386/keylocker-encodekey128.c: Likewise.
* gcc.target/i386/keylocker-encodekey256.c: Likewise.
* gcc.target/i386/keylocker-loadiwkey.c: Likewise.
* g++.dg/other/i386-2.C: Add -mkl and -mwidekl.
* g++.dg/other/i386-3.C: Likewise.
* gcc.target/i386/sse-12.c: Likewise.
* gcc.target/i386/sse-13.c: Likewise.
* gcc.target/i386/sse-14.c: Likewise.
* gcc.target/i386/sse-22.c: Add kl and widekl.
* gcc.target/i386/sse-23.c: Likewise.
* gcc.target/i386/funcspec-56.inc: Add new target attribute
test.
--
Regards,
Hongyu, Wang
[-- Attachment #2: GCC_Keylocker_support.patch --]
[-- Type: text/x-patch, Size: 80189 bytes --]
From e469649ff6e9c924964912517da69af27921a065 Mon Sep 17 00:00:00 2001
From: liuhongt <hongtao.liu@intel.com>
Date: Thu, 5 Mar 2020 17:36:02 +0800
Subject: [PATCH] Enable GCC to support Intel Key Locker ISA
gcc/ChangeLog
2018-12-15 Xuepeng Guo <xuepeng.guo@intel.com>
* common/config/i386/cpuinfo.h (get_available_features):
Detect KL, AESKLE and WIDEKL features.
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_KL_SET): New.
(OPTION_MASK_ISA_WIDEKL_SET): Likewise.
(OPTION_MASK_ISA_KL_UNSET): Likewise.
(OPTION_MASK_ISA_WIDEKL_UNSET): Likewise.
(OPTION_MASK_ISA2_AVX2_UNSET): Likewise.
(OPTION_MASK_ISA2_AVX_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE4_2_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE4_1_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE4_UNSET): Likewise.
(OPTION_MASK_ISA2_SSSE3_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE3_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE2_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE_UNSET): Likewise.
(ix86_handle_option): Handle kl and widekl, add dependency chain
for KL and SSE2.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
(FEATURE_KL, FEATURE_AESKLE, FEATURE_WIDEKL): New.
* common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY
for KL, AESKLE and WIDEKL.
* config.gcc: Add keylockerintrin.h.
* doc/invoke.texi: Document new option -mkl and -mwidekl.
* doc/extend.texi: Document kl and widekl.
* config/i386/constraints.md
(Y1, Y2, Y3, Y4, Y5, Y6, Y7): New register constraints.
* config/i386/cpuid.h (bit_KL, bit_AESKLE, bit_WIDEKL): New.
* config/i386/i386-builtin-types.def ((UINT, UINT, V2DI, V2DI, PVOID),
(UINT, UINT, V2DI, PVOID), (VOID, V2DI, V2DI, V2DI, UINT),
(UINT8, PV2DI, V2DI, PCVOID), (UINT8, PV2DI, PCV2DI, PCVOID)): New
function types.
* config/i386/i386-builtin.def: Add
__builtin_ia32_loadiwkey,
__builtin_ia32_aesdec128kl_u8,
__builtin_ia32_aesdec256kl_u8,
__builtin_ia32_aesenc128kl_u8,
__builtin_ia32_aesenc256kl_u8,
__builtin_ia32_aesdecwide128kl_u8,
__builtin_ia32_aesdecwide256kl_u8,
__builtin_ia32_aesencwide128kl_u8,
__builtin_ia32_aesencwide256kl_u8,
__builtin_ia32_encodekey128_u32,
__builtin_ia32_encodekey256_u32.
* config/i386/i386-c.c (ix86_target_macros_internal): Handle
kl and widekl.
* config/i386/i386-options.c (isa2_opts): Add -mkl and -mwidekl.
(ix86_option_override_internal): Handle KL and WIDEKL.
(ix86_valid_target_attribute_inner_p): Add attribute for kl and widekl.
* config/i386/i386-expand.c
(ix86_expand_builtin): Expand Keylocker Builtins.
* config/i386/i386.h (TARGET_KL): New.
(TARGET_KL_P): Likewise.
(TARGET_WIDEKL): Likewise.
(TARGET_WIDEKL_P): Likewise.
(PTA_KL): Likewise.
(PTA_WIDEKL): Likewise.
(enum reg_class): Add 7 new SSE register classes.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
* config/i386/i386.opt: Add new option mkl and mwidekl.
* config/i386/keylockerintrin.h: New header file for Keylocker.
* config/i386/immintrin.h: Include keylockerintrin.h.
* config/i386/sse.md (UNSPECV_LOADIWKEY): New.
(UNSPECV_AESDEC128KLU8): Likewise.
(UNSPECV_AESENC128KLU8): Likewise.
(UNSPECV_AESDEC256KLU8): Likewise.
(UNSPECV_AESENC256KLU8): Likewise.
(UNSPECV_AESDECWIDE128KLU8): Likewise.
(UNSPECV_AESENCWIDE128KLU8): Likewise.
(UNSPECV_AESDECWIDE256KLU8): Likewise.
(UNSPECV_AESENCWIDE256KLU8): Likewise.
(UNSPECV_ENCODEKEY128U32): Likewise.
(UNSPECV_ENCODEKEY256U32): Likewise.
(loadiwkey): New insn pattern.
(encodekey128u32): Likewise.
(encodekey256u32): Likewise.
(aes<aesklvariant>u8): Likewise.
(aes<aeswideklvariant>u8): Likewise.
gcc/testsuite/ChangeLog
2018-12-15 Xuepeng Guo <xuepeng.guo@intel.com>
* gcc.target/i386/keylocker-aesdec128kl.c: New test.
* gcc.target/i386/keylocker-aesdec256kl.c: Likewise.
* gcc.target/i386/keylocker-aesdecwide128kl.c: Likewise.
* gcc.target/i386/keylocker-aesdecwide256kl.c: Likewise.
* gcc.target/i386/keylocker-aesenc128kl.c: Likewise.
* gcc.target/i386/keylocker-aesencwide128kl.c: Likewise.
* gcc.target/i386/keylocker-aesencwide256kl.c: Likewise.
* gcc.target/i386/keylocker-encodekey128.c: Likewise.
* gcc.target/i386/keylocker-encodekey256.c: Likewise.
* gcc.target/i386/keylocker-loadiwkey.c: Likewise.
* g++.dg/other/i386-2.C: Add -mkl and -mwidekl.
* g++.dg/other/i386-3.C: Likewise.
* gcc.target/i386/sse-12.c: Likewise.
* gcc.target/i386/sse-13.c: Likewise.
* gcc.target/i386/sse-14.c: Likewise.
* gcc.target/i386/sse-22.c: Add kl and widekl.
* gcc.target/i386/sse-23.c: Likewise.
* gcc.target/i386/funcspec-56.inc: Add new target attribute test.
---
gcc/common/config/i386/cpuinfo.h | 19 ++
gcc/common/config/i386/i386-common.c | 86 +++++--
gcc/common/config/i386/i386-cpuinfo.h | 3 +
gcc/common/config/i386/i386-isas.h | 3 +
gcc/config.gcc | 4 +-
gcc/config/i386/constraints.md | 21 ++
gcc/config/i386/cpuid.h | 7 +
gcc/config/i386/i386-builtin-types.def | 7 +
gcc/config/i386/i386-builtin.def | 13 +
gcc/config/i386/i386-c.c | 4 +
gcc/config/i386/i386-expand.c | 237 ++++++++++++++++++
gcc/config/i386/i386-options.c | 12 +-
gcc/config/i386/i386.h | 27 ++
gcc/config/i386/i386.opt | 10 +-
gcc/config/i386/immintrin.h | 2 +
gcc/config/i386/keylockerintrin.h | 129 ++++++++++
gcc/config/i386/sse.md | 140 +++++++++++
gcc/doc/extend.texi | 10 +
gcc/doc/invoke.texi | 11 +-
gcc/testsuite/g++.dg/other/i386-2.C | 2 +-
gcc/testsuite/g++.dg/other/i386-3.C | 2 +-
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 4 +
.../gcc.target/i386/keylocker-aesdec128kl.c | 17 ++
.../gcc.target/i386/keylocker-aesdec256kl.c | 17 ++
.../i386/keylocker-aesdecwide128kl.c | 32 +++
.../i386/keylocker-aesdecwide256kl.c | 32 +++
.../gcc.target/i386/keylocker-aesenc128kl.c | 17 ++
.../i386/keylocker-aesencwide128kl.c | 32 +++
.../i386/keylocker-aesencwide256kl.c | 33 +++
.../gcc.target/i386/keylocker-encodekey128.c | 29 +++
.../gcc.target/i386/keylocker-encodekey256.c | 30 +++
.../gcc.target/i386/keylocker-loadiwkey.c | 19 ++
gcc/testsuite/gcc.target/i386/sse-12.c | 2 +-
gcc/testsuite/gcc.target/i386/sse-13.c | 2 +-
gcc/testsuite/gcc.target/i386/sse-14.c | 2 +-
gcc/testsuite/gcc.target/i386/sse-22.c | 4 +-
gcc/testsuite/gcc.target/i386/sse-23.c | 2 +-
37 files changed, 991 insertions(+), 32 deletions(-)
create mode 100644 gcc/config/i386/keylockerintrin.h
create mode 100644 gcc/testsuite/gcc.target/i386/keylocker-aesdec128kl.c
create mode 100644 gcc/testsuite/gcc.target/i386/keylocker-aesdec256kl.c
create mode 100644 gcc/testsuite/gcc.target/i386/keylocker-aesdecwide128kl.c
create mode 100644 gcc/testsuite/gcc.target/i386/keylocker-aesdecwide256kl.c
create mode 100644 gcc/testsuite/gcc.target/i386/keylocker-aesenc128kl.c
create mode 100644 gcc/testsuite/gcc.target/i386/keylocker-aesencwide128kl.c
create mode 100644 gcc/testsuite/gcc.target/i386/keylocker-aesencwide256kl.c
create mode 100644 gcc/testsuite/gcc.target/i386/keylocker-encodekey128.c
create mode 100644 gcc/testsuite/gcc.target/i386/keylocker-encodekey256.c
create mode 100644 gcc/testsuite/gcc.target/i386/keylocker-loadiwkey.c
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 12237e2f449..ea2f1d1ebcc 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -518,6 +518,8 @@ get_available_features (struct __processor_model *cpu_model,
/* Check if AVX and AVX512 are usable. */
int avx_usable = 0;
int avx512_usable = 0;
+ /* Check if KL is usable. */
+ int has_kl = 0;
if ((ecx & bit_OSXSAVE))
{
/* Check if XMM, YMM, OPMASK, upper 256 bits of ZMM0-ZMM15 and
@@ -651,6 +653,8 @@ get_available_features (struct __processor_model *cpu_model,
set_feature (FEATURE_PCONFIG);
if (edx & bit_IBT)
set_feature (FEATURE_IBT);
+ if (ecx & bit_KL)
+ has_kl = 1;
if (avx512_usable)
{
if (ebx & bit_AVX512F)
@@ -712,6 +716,21 @@ get_available_features (struct __processor_model *cpu_model,
set_feature (FEATURE_PTWRITE);
}
+ /* Get Advanced Features at level 0x19 (eax = 0x19). */
+ if (max_cpuid_level >= 0x19)
+ {
+ set_feature (FEATURE_AESKLE);
+ __cpuid (19, eax, ebx, ecx, edx);
+ /* Check if OS support keylocker. */
+ if (ebx & bit_AESKLE)
+ {
+ if (ebx & bit_WIDEKL)
+ set_feature (FEATURE_WIDEKL);
+ if (has_kl)
+ set_feature (FEATURE_KL);
+ }
+ }
+
/* Check cpuid level of extended features. */
__cpuid (0x80000000, ext_level, ebx, ecx, edx);
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 5305145a8c9..f639f378a7d 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -160,6 +160,9 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
#define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
#define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
+#define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
+#define OPTION_MASK_ISA2_WIDEKL_SET \
+ (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
/* Define a set of ISAs which aren't available when a given ISA is
disabled. MMX and SSE ISAs are handled separately. */
@@ -246,6 +249,9 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
#define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
+#define OPTION_MASK_ISA2_KL_UNSET \
+ (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
+#define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
@@ -292,6 +298,16 @@ along with GCC; see the file COPYING3. If not see
| OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET)
#define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
(OPTION_MASK_ISA2_AVX512F_UNSET)
+#define OPTION_MASK_ISA2_AVX2_UNSET OPTION_MASK_ISA2_AVX512F_UNSET
+#define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET
+#define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
+#define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
+#define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
+#define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
+#define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
+#define OPTION_MASK_ISA2_SSE2_UNSET \
+ (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
+#define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
#define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA2_AVX512BF16_UNSET
@@ -387,8 +403,8 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
- opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
- opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE_UNSET;
}
return true;
@@ -402,8 +418,8 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
- opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
- opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE2_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE2_UNSET;
}
return true;
@@ -417,8 +433,8 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
- opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
- opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE3_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE3_UNSET;
}
return true;
@@ -432,8 +448,8 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
- opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
- opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSSE3_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSSE3_UNSET;
}
return true;
@@ -447,8 +463,8 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
- opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
- opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_1_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_1_UNSET;
}
return true;
@@ -462,8 +478,8 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
- opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
- opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_2_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_2_UNSET;
}
return true;
@@ -477,8 +493,8 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
- opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
- opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX_UNSET;
}
return true;
@@ -492,8 +508,8 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
- opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
- opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX2_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX2_UNSET;
}
return true;
@@ -679,6 +695,40 @@ ix86_handle_option (struct gcc_options *opts,
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET;
}
+ return true;
+
+ case OPT_mkl:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_KL_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_SET;
+
+ /* The Keylocker instructions need XMM registers from SSE2. */
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_KL_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_UNSET;
+ }
+ return true;
+
+ case OPT_mwidekl:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WIDEKL_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_SET;
+
+ /* The Widekl instructions need XMM registers from SSE2. */
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WIDEKL_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_UNSET;
+ }
return true;
case OPT_mserialize:
@@ -964,8 +1014,8 @@ ix86_handle_option (struct gcc_options *opts,
case OPT_mno_sse4:
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
- opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
- opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_UNSET;
return true;
case OPT_msse4a:
diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
index 84ca97e7ade..2dce5126fea 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -216,6 +216,9 @@ enum processor_features
FEATURE_XSAVEC,
FEATURE_XSAVEOPT,
FEATURE_XSAVES,
+ FEATURE_KL,
+ FEATURE_AESKLE,
+ FEATURE_WIDEKL,
CPU_FEATURE_MAX
};
diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h
index 08c9dbecc76..ac768bda6c7 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -160,4 +160,7 @@ ISA_NAMES_TABLE_START
ISA_NAMES_TABLE_ENTRY("xsaveopt", FEATURE_XSAVEOPT, P_NONE,
"-mxsaveopt")
ISA_NAMES_TABLE_ENTRY("xsaves", FEATURE_XSAVES, P_NONE, "-mxsaves")
+ ISA_NAMES_TABLE_ENTRY("kl", FEATURE_KL, P_NONE, "-mkl")
+ ISA_NAMES_TABLE_ENTRY("aeskle", FEATURE_AESKLE, P_NONE, NULL)
+ ISA_NAMES_TABLE_ENTRY("widekl", FEATURE_WIDEKL, P_NONE, "-mwidekl")
ISA_NAMES_TABLE_END
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 797f0ad5edd..0da6631e897 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -412,7 +412,7 @@ i[34567]86-*-*)
waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h
avx512bf16intrin.h enqcmdintrin.h serializeintrin.h
avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h
- tsxldtrkintrin.h"
+ tsxldtrkintrin.h keylockerintrin.h"
;;
x86_64-*-*)
cpu_type=i386
@@ -447,7 +447,7 @@ x86_64-*-*)
waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h
avx512bf16intrin.h enqcmdintrin.h serializeintrin.h
avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h
- tsxldtrkintrin.h"
+ tsxldtrkintrin.h keylockerintrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index af37f5cd537..17ea97c4ac5 100644
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -115,6 +115,27 @@
(define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
"First SSE register (@code{%xmm0}).")
+(define_register_constraint "Y1" "TARGET_SSE ? SSE_SECOND_REG : NO_REGS"
+ "First SSE register (@code{%xmm1}).")
+
+(define_register_constraint "Y2" "TARGET_SSE ? SSE_THIRD_REG : NO_REGS"
+ "First SSE register (@code{%xmm2}).")
+
+(define_register_constraint "Y3" "TARGET_SSE ? SSE_FOURTH_REG : NO_REGS"
+ "First SSE register (@code{%xmm3}).")
+
+(define_register_constraint "Y4" "TARGET_SSE ? SSE_FIFTH_REG : NO_REGS"
+ "First SSE register (@code{%xmm4}).")
+
+(define_register_constraint "Y5" "TARGET_SSE ? SSE_SIXTH_REG : NO_REGS"
+ "First SSE register (@code{%xmm5}).")
+
+(define_register_constraint "Y6" "TARGET_SSE ? SSE_SEVENTH_REG : NO_REGS"
+ "First SSE register (@code{%xmm6}).")
+
+(define_register_constraint "Y7" "TARGET_SSE ? SSE_EIGHTH_REG : NO_REGS"
+ "First SSE register (@code{%xmm7}).")
+
(define_register_constraint "Yd"
"TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
"@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.")
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index bca61d620db..ccd0a918d09 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -118,6 +118,7 @@
#define bit_MOVDIR64B (1 << 28)
#define bit_ENQCMD (1 << 29)
#define bit_CLDEMOTE (1 << 25)
+#define bit_KL (1 << 23)
/* %edx */
#define bit_AVX5124VNNIW (1 << 2)
@@ -141,6 +142,12 @@
/* %ebx */
#define bit_PTWRITE (1 << 4)
+/* Keylocker leaf (%eax == 0x19) */
+/* %ebx */
+#define bit_AESKLE ( 1<<0 )
+#define bit_WIDEKL ( 1<<2 )
+
+
/* Signatures for different CPU implementations as returned in uses
of cpuid with level 0. */
#define signature_AMD_ebx 0x68747541
diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def
index 1adf7c44f4a..08044b6146f 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1285,3 +1285,10 @@ DEF_FUNCTION_TYPE (V8SF, V8SF, V16HI, V16HI)
DEF_FUNCTION_TYPE (V8SF, V8SF, V16HI, V16HI, UQI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V8HI, V8HI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V8HI, V8HI, UQI)
+
+# KEYLOCKER builtins
+DEF_FUNCTION_TYPE (UINT, UINT, V2DI, V2DI, PVOID)
+DEF_FUNCTION_TYPE (UINT, UINT, V2DI, PVOID)
+DEF_FUNCTION_TYPE (VOID, V2DI, V2DI, V2DI, UINT)
+DEF_FUNCTION_TYPE (UINT8, PV2DI, V2DI, PCVOID)
+DEF_FUNCTION_TYPE (UINT8, PV2DI, PCV2DI, PCVOID)
\ No newline at end of file
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index fec5cef0b55..985e3c46ffb 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -452,6 +452,19 @@ BDESC (0, OPTION_MASK_ISA2_SERIALIZE, CODE_FOR_serialize, "__builtin_ia32_serial
BDESC (0, OPTION_MASK_ISA2_TSXLDTRK, CODE_FOR_xsusldtrk, "__builtin_ia32_xsusldtrk", IX86_BUILTIN_XSUSLDTRK, UNKNOWN, (int) VOID_FTYPE_VOID)
BDESC (0, OPTION_MASK_ISA2_TSXLDTRK, CODE_FOR_xresldtrk, "__builtin_ia32_xresldtrk", IX86_BUILTIN_XRESLDTRK, UNKNOWN, (int) VOID_FTYPE_VOID)
+/* KEYLOCKER */
+BDESC (0, OPTION_MASK_ISA2_KL, CODE_FOR_loadiwkey, "__builtin_ia32_loadiwkey", IX86_BUILTIN_LOADIWKEY, UNKNOWN, (int) VOID_FTYPE_V2DI_V2DI_V2DI_UINT)
+BDESC (0, OPTION_MASK_ISA2_KL, CODE_FOR_aesdec128klu8, "__builtin_ia32_aesdec128kl_u8", IX86_BUILTIN_AESDEC128KLU8, UNKNOWN, (int) UINT8_FTYPE_PV2DI_V2DI_PCVOID)
+BDESC (0, OPTION_MASK_ISA2_KL, CODE_FOR_aesdec256klu8, "__builtin_ia32_aesdec256kl_u8", IX86_BUILTIN_AESDEC256KLU8, UNKNOWN, (int) UINT8_FTYPE_PV2DI_V2DI_PCVOID)
+BDESC (0, OPTION_MASK_ISA2_KL, CODE_FOR_aesenc128klu8, "__builtin_ia32_aesenc128kl_u8", IX86_BUILTIN_AESENC128KLU8, UNKNOWN, (int) UINT8_FTYPE_PV2DI_V2DI_PCVOID)
+BDESC (0, OPTION_MASK_ISA2_KL, CODE_FOR_aesenc256klu8, "__builtin_ia32_aesenc256kl_u8", IX86_BUILTIN_AESENC256KLU8, UNKNOWN, (int) UINT8_FTYPE_PV2DI_V2DI_PCVOID)
+BDESC (0, OPTION_MASK_ISA2_KL, CODE_FOR_encodekey128u32, "__builtin_ia32_encodekey128_u32", IX86_BUILTIN_ENCODEKEY128U32, UNKNOWN, (int) UINT_FTYPE_UINT_V2DI_PVOID)
+BDESC (0, OPTION_MASK_ISA2_KL, CODE_FOR_encodekey256u32, "__builtin_ia32_encodekey256_u32", IX86_BUILTIN_ENCODEKEY256U32, UNKNOWN, (int) UINT_FTYPE_UINT_V2DI_V2DI_PVOID)
+BDESC (0, OPTION_MASK_ISA2_WIDEKL, CODE_FOR_aesdecwide128klu8, "__builtin_ia32_aesdecwide128kl_u8", IX86_BUILTIN_AESDECWIDE128KLU8, UNKNOWN, (int) UINT8_FTYPE_PV2DI_PCV2DI_PCVOID)
+BDESC (0, OPTION_MASK_ISA2_WIDEKL, CODE_FOR_aesdecwide256klu8, "__builtin_ia32_aesdecwide256kl_u8", IX86_BUILTIN_AESDECWIDE256KLU8, UNKNOWN, (int) UINT8_FTYPE_PV2DI_PCV2DI_PCVOID)
+BDESC (0, OPTION_MASK_ISA2_WIDEKL, CODE_FOR_aesencwide128klu8, "__builtin_ia32_aesencwide128kl_u8", IX86_BUILTIN_AESENCWIDE128KLU8, UNKNOWN, (int) UINT8_FTYPE_PV2DI_PCV2DI_PCVOID)
+BDESC (0, OPTION_MASK_ISA2_WIDEKL, CODE_FOR_aesencwide256klu8, "__builtin_ia32_aesencwide256kl_u8", IX86_BUILTIN_AESENCWIDE256KLU8, UNKNOWN, (int) UINT8_FTYPE_PV2DI_PCV2DI_PCVOID)
+
BDESC_END (SPECIAL_ARGS, ARGS)
/* Builtins with variable number of arguments. */
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 3553a372427..c268d6df3af 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -588,6 +588,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__ENQCMD__");
if (isa_flag2 & OPTION_MASK_ISA2_TSXLDTRK)
def_or_undef (parse_in, "__TSXLDTRK__");
+ if (isa_flag2 & OPTION_MASK_ISA2_KL)
+ def_or_undef (parse_in, "__KL__");
+ if (isa_flag2 & OPTION_MASK_ISA2_WIDEKL)
+ def_or_undef (parse_in, "__WIDEKL__");
if (TARGET_IAMCU)
{
def_or_undef (parse_in, "__iamcu");
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index e6f8b314f18..ff6bfdb5348 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -11221,6 +11221,243 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
emit_insn (gen_cldemote (op0));
return 0;
+ case IX86_BUILTIN_LOADIWKEY:
+ {
+ arg0 = CALL_EXPR_ARG (exp, 0);
+ arg1 = CALL_EXPR_ARG (exp, 1);
+ arg2 = CALL_EXPR_ARG (exp, 2);
+ arg3 = CALL_EXPR_ARG (exp, 3);
+
+ op0 = expand_normal (arg0);
+ op1 = expand_normal (arg1);
+ op2 = expand_normal (arg2);
+ op3 = expand_normal (arg3);
+
+ if (!REG_P (op0))
+ op0 = copy_to_mode_reg (V2DImode, op0);
+ if (!REG_P (op1))
+ op1 = copy_to_mode_reg (V2DImode, op1);
+ if (!REG_P (op2))
+ op2 = copy_to_mode_reg (V2DImode, op2);
+ if (!REG_P (op3))
+ op3 = copy_to_mode_reg (SImode, op3);
+
+ emit_insn (gen_loadiwkey (op0, op1, op2, op3));
+
+ return 0;
+ }
+
+ case IX86_BUILTIN_AESDEC128KLU8:
+ icode = CODE_FOR_aesdec128klu8;
+ goto aesdecenc_expand;
+
+ case IX86_BUILTIN_AESDEC256KLU8:
+ icode = CODE_FOR_aesdec256klu8;
+ goto aesdecenc_expand;
+
+ case IX86_BUILTIN_AESENC128KLU8:
+ icode = CODE_FOR_aesenc128klu8;
+ goto aesdecenc_expand;
+
+ case IX86_BUILTIN_AESENC256KLU8:
+ icode = CODE_FOR_aesenc256klu8;
+
+ aesdecenc_expand:
+
+ arg0 = CALL_EXPR_ARG (exp, 0); // __m128i *odata
+ arg1 = CALL_EXPR_ARG (exp, 1); // __m128i idata
+ arg2 = CALL_EXPR_ARG (exp, 2); // const void *p
+
+ op0 = expand_normal (arg0);
+ op1 = expand_normal (arg1);
+ op2 = expand_normal (arg2);
+
+ if (!address_operand (op0, V2DImode))
+ {
+ op0 = convert_memory_address (Pmode, op0);
+ op0 = copy_addr_to_reg (op0);
+ }
+ op0 = gen_rtx_MEM (V2DImode, op0);
+
+ if (!REG_P (op1))
+ op1 = copy_to_mode_reg (V2DImode, op1);
+
+ if (!address_operand (op2, VOIDmode))
+ {
+ op2 = convert_memory_address (Pmode, op2);
+ op2 = copy_addr_to_reg (op2);
+ }
+ op2 = gen_rtx_MEM (BLKmode, op2);
+
+ emit_insn (GEN_FCN (icode) (op1, op1, op2));
+
+ if (target == 0)
+ target = gen_reg_rtx (QImode);
+
+ pat = gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
+ const0_rtx);
+ emit_insn (gen_rtx_SET (target, pat));
+
+ emit_insn (gen_rtx_SET (op0, op1));
+
+ return target;
+
+ case IX86_BUILTIN_AESDECWIDE128KLU8:
+ icode = CODE_FOR_aesdecwide128klu8;
+ goto wideaesdecenc_expand;
+
+ case IX86_BUILTIN_AESDECWIDE256KLU8:
+ icode = CODE_FOR_aesdecwide256klu8;
+ goto wideaesdecenc_expand;
+
+ case IX86_BUILTIN_AESENCWIDE128KLU8:
+ icode = CODE_FOR_aesencwide128klu8;
+ goto wideaesdecenc_expand;
+
+ case IX86_BUILTIN_AESENCWIDE256KLU8:
+ icode = CODE_FOR_aesencwide256klu8;
+
+ wideaesdecenc_expand:
+
+ rtx xmm_regs[8];
+ rtx op;
+
+ arg0 = CALL_EXPR_ARG (exp, 0); // __m128i * odata
+ arg1 = CALL_EXPR_ARG (exp, 1); // const __m128i * idata
+ arg2 = CALL_EXPR_ARG (exp, 2); // const void *p
+
+ op0 = expand_normal (arg0);
+ op1 = expand_normal (arg1);
+ op2 = expand_normal (arg2);
+
+ if (!address_operand (op2, VOIDmode))
+ {
+ op2 = convert_memory_address (Pmode, op2);
+ op2 = copy_addr_to_reg (op2);
+ }
+ op2 = gen_rtx_MEM (BLKmode, op2);
+
+ for (i = 0; i < 8; i++)
+ {
+ xmm_regs[i] = gen_reg_rtx (V2DImode);
+
+ op = gen_rtx_MEM (V2DImode,
+ plus_constant (Pmode, op1, (i * 16)));
+
+ emit_move_insn (xmm_regs[i], op);
+ }
+
+ emit_insn (GEN_FCN (icode) (op2,
+ xmm_regs[0], xmm_regs[1],
+ xmm_regs[2], xmm_regs[3],
+ xmm_regs[4], xmm_regs[5],
+ xmm_regs[6], xmm_regs[7],
+ xmm_regs[0], xmm_regs[1],
+ xmm_regs[2], xmm_regs[3],
+ xmm_regs[4], xmm_regs[5],
+ xmm_regs[6], xmm_regs[7]));
+
+ if (target == 0)
+ target = gen_reg_rtx (QImode);
+
+ pat = gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
+ const0_rtx);
+ emit_move_insn (target, pat);
+
+ for (i = 0; i < 8; i++)
+ {
+ op = gen_rtx_MEM (V2DImode,
+ plus_constant (Pmode, op1, (i * 16)));
+ emit_move_insn (op, xmm_regs[i]);
+ }
+
+ return target;
+
+ case IX86_BUILTIN_ENCODEKEY128U32:
+ {
+ rtx op, xmm_regs[6];
+
+ arg0 = CALL_EXPR_ARG (exp, 0); // unsigned int htype
+ arg1 = CALL_EXPR_ARG (exp, 1); // __m128i key
+ arg2 = CALL_EXPR_ARG (exp, 2); // void *h
+
+ op0 = expand_normal (arg0);
+ op1 = expand_normal (arg1);
+ op2 = expand_normal (arg2);
+
+ if (!REG_P (op0))
+ op0 = copy_to_mode_reg (SImode, op0);
+ if (!REG_P (op1))
+ op1 = copy_to_mode_reg (V2DImode, op1);
+
+ xmm_regs[0] = op1;
+ for (i = 1; i < 6; i++)
+ xmm_regs[i] = gen_reg_rtx (V2DImode);
+
+ if (target == 0)
+ target = gen_reg_rtx (SImode);
+
+ emit_insn (gen_encodekey128u32 (target, op0,
+ xmm_regs[0], xmm_regs[0],
+ xmm_regs[1], xmm_regs[2],
+ xmm_regs[3], xmm_regs[4],
+ xmm_regs[5]));
+
+ for (i = 0; i < 3; i++)
+ {
+ op = gen_rtx_MEM (V2DImode,
+ plus_constant (Pmode, op2, (i * 16)));
+ emit_move_insn (op, xmm_regs[i]);
+ }
+
+ return target;
+ }
+ case IX86_BUILTIN_ENCODEKEY256U32:
+ {
+ rtx op, xmm_regs[7];
+
+ arg0 = CALL_EXPR_ARG (exp, 0); // unsigned int htype
+ arg1 = CALL_EXPR_ARG (exp, 1); // __m128i keylow
+ arg2 = CALL_EXPR_ARG (exp, 2); // __m128i keyhi
+ arg3 = CALL_EXPR_ARG (exp, 3); // void *h
+
+ op0 = expand_normal (arg0);
+ op1 = expand_normal (arg1);
+ op2 = expand_normal (arg2);
+ op3 = expand_normal (arg3);
+
+ if (!REG_P (op0))
+ op0 = copy_to_mode_reg (SImode, op0);
+ if (!REG_P (op1))
+ op1 = copy_to_mode_reg (V2DImode, op1);
+ if (!REG_P (op2))
+ op2 = copy_to_mode_reg (V2DImode, op2);
+
+ xmm_regs[0] = op1;
+ xmm_regs[1] = op2;
+ for (i = 2; i < 7; i++)
+ xmm_regs[i] = gen_reg_rtx (V2DImode);
+
+ if (target == 0)
+ target = gen_reg_rtx (SImode);
+
+ emit_insn (gen_encodekey256u32 (target, op0,
+ xmm_regs[0], xmm_regs[1],
+ xmm_regs[0], xmm_regs[1],
+ xmm_regs[2], xmm_regs[3],
+ xmm_regs[4], xmm_regs[5],
+ xmm_regs[6]));
+
+ for (i = 0; i < 4; i++)
+ {
+ op = gen_rtx_MEM (V2DImode,
+ plus_constant (Pmode, op3, (i * 16)));
+ emit_move_insn (op, xmm_regs[i]);
+ }
+
+ return target;
+ }
+
case IX86_BUILTIN_VEC_INIT_V2SI:
case IX86_BUILTIN_VEC_INIT_V4HI:
case IX86_BUILTIN_VEC_INIT_V8QI:
diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c
index 2fabd200298..c4b8065a8cb 100644
--- a/gcc/config/i386/i386-options.c
+++ b/gcc/config/i386/i386-options.c
@@ -209,7 +209,9 @@ static struct ix86_target_opts isa2_opts[] =
{ "-mavx512bf16", OPTION_MASK_ISA2_AVX512BF16 },
{ "-menqcmd", OPTION_MASK_ISA2_ENQCMD },
{ "-mserialize", OPTION_MASK_ISA2_SERIALIZE },
- { "-mtsxldtrk", OPTION_MASK_ISA2_TSXLDTRK }
+ { "-mtsxldtrk", OPTION_MASK_ISA2_TSXLDTRK },
+ { "-mkl", OPTION_MASK_ISA2_KL },
+ { "-mwidekl", OPTION_MASK_ISA2_WIDEKL },
};
static struct ix86_target_opts isa_opts[] =
{
@@ -1029,6 +1031,8 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
IX86_ATTR_ISA ("waitpkg", OPT_mwaitpkg),
IX86_ATTR_ISA ("cldemote", OPT_mcldemote),
IX86_ATTR_ISA ("ptwrite", OPT_mptwrite),
+ IX86_ATTR_ISA ("kl", OPT_mkl),
+ IX86_ATTR_ISA ("widekl", OPT_mwidekl),
IX86_ATTR_ISA ("avx512bf16", OPT_mavx512bf16),
IX86_ATTR_ISA ("enqcmd", OPT_menqcmd),
IX86_ATTR_ISA ("serialize", OPT_mserialize),
@@ -2297,6 +2301,12 @@ ix86_option_override_internal (bool main_args_p,
if (((processor_alias_table[i].flags & PTA_TSXLDTRK) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_TSXLDTRK))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TSXLDTRK;
+ if (((processor_alias_table[i].flags & PTA_KL) != 0)
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_KL))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_KL;
+ if (((processor_alias_table[i].flags & PTA_WIDEKL) != 0)
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_WIDEKL))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WIDEKL;
if ((processor_alias_table[i].flags
& (PTA_PREFETCH_SSE | PTA_SSE)) != 0)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 92b7475a7bf..e1c084c5d36 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -203,6 +203,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define TARGET_SERIALIZE_P(x) TARGET_ISA2_SERIALIZE_P(x)
#define TARGET_TSXLDTRK TARGET_ISA2_TSXLDTRK
#define TARGET_TSXLDTRK_P(x) TARGET_ISA2_TSXLDTRK_P(x)
+#define TARGET_KL TARGET_ISA2_KL
+#define TARGET_KL_P(x) TARGET_ISA2_KL_P(x)
+#define TARGET_WIDEKL TARGET_ISA2_WIDEKL
+#define TARGET_WIDEKL_P(x) TARGET_ISA2_WIDEKL_P(x)
#define TARGET_LP64 TARGET_ABI_64
#define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
@@ -1408,6 +1412,13 @@ enum reg_class
FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
FLOAT_REGS,
SSE_FIRST_REG,
+ SSE_SECOND_REG,
+ SSE_THIRD_REG,
+ SSE_FOURTH_REG,
+ SSE_FIFTH_REG,
+ SSE_SIXTH_REG,
+ SSE_SEVENTH_REG,
+ SSE_EIGHTH_REG,
NO_REX_SSE_REGS,
SSE_REGS,
ALL_SSE_REGS,
@@ -1468,6 +1479,13 @@ enum reg_class
"FP_TOP_REG", "FP_SECOND_REG", \
"FLOAT_REGS", \
"SSE_FIRST_REG", \
+ "SSE_SECOND_REG", \
+ "SSE_THIRD_REG", \
+ "SSE_FOURTH_REG", \
+ "SSE_FIFTH_REG", \
+ "SSE_SIXTH_REG", \
+ "SSE_SEVENTH_REG", \
+ "SSE_EIGHTH_REG", \
"NO_REX_SSE_REGS", \
"SSE_REGS", \
"ALL_SSE_REGS", \
@@ -1507,6 +1525,13 @@ enum reg_class
{ 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
{ 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
{ 0x100000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
+ { 0x200000, 0x0, 0x0 }, /* SSE_SECOND_REG */ \
+ { 0x400000, 0x0, 0x0 }, /* SSE_THIRD_REG */ \
+ { 0x800000, 0x0, 0x0 }, /* SSE_FOURTH_REG */ \
+ { 0x1000000, 0x0, 0x0 }, /* SSE_FIFTH_REG */ \
+ { 0x2000000, 0x0, 0x0 }, /* SSE_SIXTH_REG*/ \
+ { 0x4000000, 0x0, 0x0 }, /* SSE_SEVENTH_REG */ \
+ { 0x8000000, 0x0, 0x0 }, /* SSE_EIGHTH_REG */ \
{ 0xff00000, 0x0, 0x0 }, /* NO_REX_SSE_REGS */ \
{ 0xff00000, 0xff000, 0x0 }, /* SSE_REGS */ \
{ 0xff00000, 0xfffff000, 0xf }, /* ALL_SSE_REGS */ \
@@ -2466,6 +2491,8 @@ const wide_int_bitmask PTA_ENQCMD (0, HOST_WIDE_INT_1U << 15);
const wide_int_bitmask PTA_CLDEMOTE (0, HOST_WIDE_INT_1U << 16);
const wide_int_bitmask PTA_SERIALIZE (0, HOST_WIDE_INT_1U << 17);
const wide_int_bitmask PTA_TSXLDTRK (0, HOST_WIDE_INT_1U << 18);
+const wide_int_bitmask PTA_KL (0, HOST_WIDE_INT_1U << 22);
+const wide_int_bitmask PTA_WIDEKL (0, HOST_WIDE_INT_1U << 23);
const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
| PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index c9f7195d423..d22283818a9 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1114,4 +1114,12 @@ Support SERIALIZE built-in functions and code generation.
mtsxldtrk
Target Report Mask(ISA2_TSXLDTRK) Var(ix86_isa_flags2) Save
-Support TSXLDTRK built-in functions and code generation.
\ No newline at end of file
+Support TSXLDTRK built-in functions and code generation.
+
+mkl
+Target Report Mask(ISA2_KL) Var(ix86_isa_flags2) Save
+Support KL built-in functions and code generation.
+
+mwidekl
+Target Report Mask(ISA2_WIDEKL) Var(ix86_isa_flags2) Save
+Support WIDEKL built-in functions and code generation.
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index b660d0d9040..3684f505d5a 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -158,6 +158,8 @@
#include <pkuintrin.h>
+#include <keylockerintrin.h>
+
extern __inline void
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_wbinvd (void)
diff --git a/gcc/config/i386/keylockerintrin.h b/gcc/config/i386/keylockerintrin.h
new file mode 100644
index 00000000000..a5f29fdcba9
--- /dev/null
+++ b/gcc/config/i386/keylockerintrin.h
@@ -0,0 +1,129 @@
+/* Copyright (C) 2018 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#if !defined _IMMINTRIN_H_INCLUDED
+# error "Never use <keylockerintrin.h> directly; include <x86intrin.h> instead."
+#endif
+
+#ifndef _KEYLOCKERINTRIN_H_INCLUDED
+#define _KEYLOCKERINTRIN_H_INCLUDED
+
+#ifndef __KL__
+#pragma GCC push_options
+#pragma GCC target("kl")
+#define __DISABLE_KL__
+#endif /* __KL__ */
+
+
+extern __inline
+void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_loadiwkey (unsigned int __I, __m128i __A, __m128i __B, __m128i __C)
+{
+ __builtin_ia32_loadiwkey ((__v2di) __B, (__v2di) __C, (__v2di) __A, __I);
+}
+
+extern __inline
+unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_encodekey128_u32 (unsigned int __I, __m128i __A, void * __P)
+{
+ return __builtin_ia32_encodekey128_u32 (__I, (__v2di)__A, __P);
+}
+
+extern __inline
+unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_encodekey256_u32 (unsigned int __I, __m128i __A, __m128i __B, void * __P)
+{
+ return __builtin_ia32_encodekey256_u32 (__I, (__v2di)__A, (__v2di)__B, __P);
+}
+
+extern __inline
+unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_aesdec128kl_u8 (__m128i * __A, __m128i __B, const void * __P)
+{
+ return __builtin_ia32_aesdec128kl_u8 ((__v2di *) __A, (__v2di) __B, __P);
+}
+
+extern __inline
+unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_aesdec256kl_u8 (__m128i * __A, __m128i __B, const void * __P)
+{
+ return __builtin_ia32_aesdec256kl_u8 ((__v2di *) __A, (__v2di) __B, __P);
+}
+
+extern __inline
+unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_aesenc128kl_u8 (__m128i * __A, __m128i __B, const void * __P)
+{
+ return __builtin_ia32_aesenc128kl_u8 ((__v2di *) __A, (__v2di) __B, __P);
+}
+
+extern __inline
+unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_aesenc256kl_u8 (__m128i * __A, __m128i __B, const void * __P)
+{
+ return __builtin_ia32_aesenc256kl_u8 ((__v2di *) __A, (__v2di) __B, __P);
+}
+
+#ifdef __DISABLE_KL__
+#undef __DISABLE_KL__
+#pragma GCC pop_options
+#endif /* __DISABLE_KL__ */
+
+#ifndef __WIDEKL__
+#pragma GCC push_options
+#pragma GCC target("widekl")
+#define __DISABLE_WIDEKL__
+#endif /* __WIDEKL__ */
+
+extern __inline
+unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_aesdecwide128kl_u8(__m128i __A[8], const __m128i __B[8], const void * __P)
+{
+ return __builtin_ia32_aesdecwide128kl_u8 ((__v2di *) __A, (__v2di *) __B, __P);
+}
+
+extern __inline
+unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_aesdecwide256kl_u8(__m128i __A[8], const __m128i __B[8], const void * __P)
+{
+ return __builtin_ia32_aesdecwide256kl_u8 ((__v2di *) __A, (__v2di *) __B, __P);
+}
+
+extern __inline
+unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_aesencwide128kl_u8(__m128i __A[8], const __m128i __B[8], const void * __P)
+{
+ return __builtin_ia32_aesencwide128kl_u8 ((__v2di *) __A, (__v2di *) __B, __P);
+}
+
+extern __inline
+unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_aesencwide256kl_u8(__m128i __A[8], const __m128i __B[8], const void * __P)
+{
+ return __builtin_ia32_aesencwide256kl_u8 ((__v2di *) __A, (__v2di *) __B, __P);
+}
+#ifdef __DISABLE_WIDEKL__
+#undef __DISABLE_WIDEKL__
+#pragma GCC pop_options
+#endif /* __DISABLE_WIDEKL__ */
+#endif /* _KEYLOCKERINTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index a784346a23b..77ac1b54281 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -205,6 +205,19 @@
UNSPECV_MWAIT
UNSPECV_VZEROALL
UNSPECV_VZEROUPPER
+
+ ;; For KEYLOCKER
+ UNSPECV_LOADIWKEY
+ UNSPECV_AESDEC128KLU8
+ UNSPECV_AESENC128KLU8
+ UNSPECV_AESDEC256KLU8
+ UNSPECV_AESENC256KLU8
+ UNSPECV_AESDECWIDE128KLU8
+ UNSPECV_AESENCWIDE128KLU8
+ UNSPECV_AESDECWIDE256KLU8
+ UNSPECV_AESENCWIDE256KLU8
+ UNSPECV_ENCODEKEY128U32
+ UNSPECV_ENCODEKEY256U32
])
;; All vector modes including V?TImode, used in move patterns.
@@ -23613,3 +23626,130 @@
(match_operand:<avx512fmaskhalfmode> 4 "register_operand" "Yk")))]
"TARGET_AVX512BF16"
"vdpbf16ps\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}")
+
+;; KEYLOCKER
+(define_insn "loadiwkey"
+ [(unspec_volatile:V2DI [(match_operand:V2DI 0 "register_operand" "v")
+ (match_operand:V2DI 1 "register_operand" "v")
+ (match_operand:V2DI 2 "register_operand" "Yz")
+ (match_operand:SI 3 "register_operand" "a")]
+ UNSPECV_LOADIWKEY)
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_KL"
+ "loadiwkey\t{%0, %1|%1, %0}"
+ [(set_attr "type" "other")])
+
+(define_insn "encodekey128u32"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:V2DI 3 "register_operand" "2")]
+ UNSPECV_ENCODEKEY128U32))
+ (set (match_operand:V2DI 2 "register_operand" "=Yz")
+ (unspec_volatile:V2DI [(match_dup 1) (match_dup 3)]
+ UNSPECV_ENCODEKEY128U32))
+ (set (match_operand:V2DI 4 "register_operand" "=Y1")
+ (unspec_volatile:V2DI [(match_dup 1) (match_dup 3)]
+ UNSPECV_ENCODEKEY128U32))
+ (set (match_operand:V2DI 5 "register_operand" "=Y2")
+ (unspec_volatile:V2DI [(match_dup 1) (match_dup 3)]
+ UNSPECV_ENCODEKEY128U32))
+ (set (match_operand:V2DI 6 "register_operand" "=Y4")
+ (const_vector:V2DI [(const_int 0) (const_int 0)]))
+ (set (match_operand:V2DI 7 "register_operand" "=Y5")
+ (const_vector:V2DI [(const_int 0) (const_int 0)]))
+ (set (match_operand:V2DI 8 "register_operand" "=Y6")
+ (const_vector:V2DI [(const_int 0) (const_int 0)]))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_KL"
+ "encodekey128\t{%1, %0|%0, %1}"
+ [(set_attr "type" "other")])
+
+(define_insn "encodekey256u32"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:V2DI 4 "register_operand" "2")
+ (match_operand:V2DI 5 "register_operand" "3")]
+ UNSPECV_ENCODEKEY256U32))
+ (set (match_operand:V2DI 2 "register_operand" "=Yz")
+ (unspec_volatile:V2DI [(match_dup 1) (match_dup 4) (match_dup 5)]
+ UNSPECV_ENCODEKEY256U32))
+ (set (match_operand:V2DI 3 "register_operand" "=Y1")
+ (unspec_volatile:V2DI [(match_dup 1) (match_dup 4) (match_dup 5)]
+ UNSPECV_ENCODEKEY256U32))
+ (set (match_operand:V2DI 6 "register_operand" "=Y2")
+ (unspec_volatile:V2DI [(match_dup 1) (match_dup 4) (match_dup 5)]
+ UNSPECV_ENCODEKEY256U32))
+ (set (match_operand:V2DI 7 "register_operand" "=Y3")
+ (unspec_volatile:V2DI [(match_dup 1) (match_dup 4) (match_dup 5)]
+ UNSPECV_ENCODEKEY256U32))
+ (set (match_operand:V2DI 8 "register_operand" "=Y4")
+ (const_vector:V2DI [(const_int 0) (const_int 0)]))
+ (set (match_operand:V2DI 9 "register_operand" "=Y5")
+ (const_vector:V2DI [(const_int 0) (const_int 0)]))
+ (set (match_operand:V2DI 10 "register_operand" "=Y6")
+ (const_vector:V2DI [(const_int 0) (const_int 0)]))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_KL"
+ "encodekey256\t{%1, %0|%0, %1}"
+ [(set_attr "type" "other")])
+
+(define_int_iterator AESDECENCKL [UNSPECV_AESDEC128KLU8 UNSPECV_AESDEC256KLU8
+ UNSPECV_AESENC128KLU8 UNSPECV_AESENC256KLU8])
+
+(define_int_attr aesklvariant [(UNSPECV_AESDEC128KLU8 "dec128kl")
+ (UNSPECV_AESDEC256KLU8 "dec256kl")
+ (UNSPECV_AESENC128KLU8 "enc128kl")
+ (UNSPECV_AESENC256KLU8 "enc256kl")])
+
+(define_insn "aes<aesklvariant>u8"
+ [(set (match_operand:V2DI 0 "register_operand" "=v")
+ (unspec_volatile:V2DI [(match_operand:V2DI 1 "register_operand" "0")
+ (match_operand:BLK 2 "memory_operand" "m")]
+ AESDECENCKL))
+ (set (reg:CCZ FLAGS_REG)
+ (unspec_volatile:CCZ [(match_dup 1) (match_dup 2)] AESDECENCKL))]
+ "TARGET_KL"
+ "aes<aesklvariant>\t{%2, %0|%0, %2}"
+ [(set_attr "type" "other")])
+
+(define_int_iterator AESDECENCWIDEKL [UNSPECV_AESDECWIDE128KLU8 UNSPECV_AESDECWIDE256KLU8
+ UNSPECV_AESENCWIDE128KLU8 UNSPECV_AESENCWIDE256KLU8])
+
+(define_int_attr aeswideklvariant [(UNSPECV_AESDECWIDE128KLU8 "decwide128kl")
+ (UNSPECV_AESDECWIDE256KLU8 "decwide256kl")
+ (UNSPECV_AESENCWIDE128KLU8 "encwide128kl")
+ (UNSPECV_AESENCWIDE256KLU8 "encwide256kl")])
+
+(define_insn "aes<aeswideklvariant>u8"
+ [(set (reg:CCZ FLAGS_REG)
+ (unspec_volatile:CCZ [(match_operand:BLK 0 "memory_operand" "m")
+ (match_operand:V2DI 9 "register_operand" "1")
+ (match_operand:V2DI 10 "register_operand" "2")
+ (match_operand:V2DI 11 "register_operand" "3")
+ (match_operand:V2DI 12 "register_operand" "4")
+ (match_operand:V2DI 13 "register_operand" "5")
+ (match_operand:V2DI 14 "register_operand" "6")
+ (match_operand:V2DI 15 "register_operand" "7")
+ (match_operand:V2DI 16 "register_operand" "8")]
+ AESDECENCWIDEKL))
+ (set (match_operand:V2DI 1 "register_operand" "=Yz")
+ (unspec_volatile:V2DI [(const_int 0)] AESDECENCWIDEKL))
+ (set (match_operand:V2DI 2 "register_operand" "=Y1")
+ (unspec_volatile:V2DI [(const_int 0)] AESDECENCWIDEKL))
+ (set (match_operand:V2DI 3 "register_operand" "=Y2")
+ (unspec_volatile:V2DI [(const_int 0)] AESDECENCWIDEKL))
+ (set (match_operand:V2DI 4 "register_operand" "=Y3")
+ (unspec_volatile:V2DI [(const_int 0)] AESDECENCWIDEKL))
+ (set (match_operand:V2DI 5 "register_operand" "=Y4")
+ (unspec_volatile:V2DI [(const_int 0)] AESDECENCWIDEKL))
+ (set (match_operand:V2DI 6 "register_operand" "=Y5")
+ (unspec_volatile:V2DI [(const_int 0)] AESDECENCWIDEKL))
+ (set (match_operand:V2DI 7 "register_operand" "=Y6")
+ (unspec_volatile:V2DI [(const_int 0)] AESDECENCWIDEKL))
+ (set (match_operand:V2DI 8 "register_operand" "=Y7")
+ (unspec_volatile:V2DI [(const_int 0)] AESDECENCWIDEKL))]
+ "TARGET_WIDEKL"
+ "aes<aeswideklvariant>\t{%0}"
+ [(set_attr "type" "other")])
\ No newline at end of file
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 3b37aba5795..f2d5425730f 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -6623,6 +6623,16 @@ Enable/disable the generation of the XSAVEOPT instructions.
@cindex @code{target("xsaves")} function attribute, x86
Enable/disable the generation of the XSAVES instructions.
+@item kl
+@itemx no-kl
+@cindex @code{target("kl")} function attribute, x86
+Enable/disable the generation of the KEYLOCKER instructions.
+
+@item widekl
+@itemx no-widekl
+@cindex @code{target("widekl")} function attribute, x86
+Enable/disable the generation of the WIDEKL instructions.
+
@item cld
@itemx no-cld
@cindex @code{target("cld")} function attribute, x86
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6d9ff2c3362..4973a992971 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1361,6 +1361,7 @@ See RS/6000 and PowerPC Options.
-mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk@gol
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops @gol
-minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol
+-mkl -mwidekl @gol
-mmemcpy-strategy=@var{strategy} -mmemset-strategy=@var{strategy} @gol
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
-m96bit-long-double -mlong-double-64 -mlong-double-80 -mlong-double-128 @gol
@@ -30035,6 +30036,12 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@need 200
@itemx -mserialize
@opindex mserialize
+@need 200
+@itemx -mkl
+@opindex mkl
+@need 200
+@itemx -mwidekl
+@opindex mwidekl
These switches enable the use of instructions in the MMX, SSE,
SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF,
AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
@@ -30044,8 +30051,8 @@ WBNOINVD, FMA4, PREFETCHW, RDPID, PREFETCHWT1, RDSEED, SGX, XOP, LWP,
XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2,
GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE
-or CLDEMOTE extended instruction sets. Each has a corresponding
-@option{-mno-} option to disable use of these instructions.
+KL, WIDEKL or CLDEMOTE extended instruction sets. Each has
+a corresponding @option{-mno-} option to disable use of these instructions.
These extensions are also available as built-in functions: see
@ref{x86 Built-in Functions}, for details of the functions enabled and
diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C
index 04d5fec0f6c..ec3ed844351 100644
--- a/gcc/testsuite/g++.dg/other/i386-2.C
+++ b/gcc/testsuite/g++.dg/other/i386-2.C
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mkl -mwidekl" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C
index f40172ee9b5..418c3d323de 100644
--- a/gcc/testsuite/g++.dg/other/i386-3.C
+++ b/gcc/testsuite/g++.dg/other/i386-3.C
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mkl -mwidekl" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index 94ffbb64c75..1028ebac1ec 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -71,6 +71,8 @@ extern void test_tsxldtrk (void) __attribute__((__target__("tsxldtrk")));
extern void test_enqcmd (void) __attribute__((__target__("enqcmd")));
extern void test_avx512bf16 (void) __attribute__((__target__("avx512bf16")));
extern void test_avx512vp2intersect (void) __attribute__((__target__("avx512vp2intersect")));
+extern void test_keylocker (void) __attribute__((__target__("kl")));
+extern void test_widekl (void) __attribute__((__target__("widekl")));
extern void test_no_sgx (void) __attribute__((__target__("no-sgx")));
extern void test_no_avx5124fmaps(void) __attribute__((__target__("no-avx5124fmaps")));
@@ -143,6 +145,8 @@ extern void test_no_tsxldtrk (void) __attribute__((__target__("no-tsxldtrk")));
extern void test_no_enqcmd (void) __attribute__((__target__("no-enqcmd")));
extern void test_no_avx512bf16 (void) __attribute__((__target__("no-avx512bf16")));
extern void test_no_avx512vp2intersect (void) __attribute__((__target__("no-avx512vp2intersect")));
+extern void test_no_keylocker (void) __attribute__((__target__("no-kl")));
+extern void test_no_widekl (void) __attribute__((__target__("no-widekl")));
extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona")));
extern void test_arch_core2 (void) __attribute__((__target__("arch=core2")));
diff --git a/gcc/testsuite/gcc.target/i386/keylocker-aesdec128kl.c b/gcc/testsuite/gcc.target/i386/keylocker-aesdec128kl.c
new file mode 100644
index 00000000000..3cdda8ed7b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/keylocker-aesdec128kl.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mkl -O2" } */
+/* { dg-final { scan-assembler "movdqa\[ \\t\]+\[^\n\]*k2\[^\n\r]*%xmm0" } } */
+/* { dg-final { scan-assembler "aesdec128kl\[ \\t\]+\[^\n\]*h1\[^\n\r]*%xmm0" } } */
+/* { dg-final { scan-assembler "sete" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm0\[^\n\r]*k1" } } */
+
+#include <immintrin.h>
+
+__m128i k1, k2;
+const char h1[48];
+
+unsigned char
+test_keylocker_1 (void)
+{
+ return _mm_aesdec128kl_u8 (&k1, k2, h1);
+}
diff --git a/gcc/testsuite/gcc.target/i386/keylocker-aesdec256kl.c b/gcc/testsuite/gcc.target/i386/keylocker-aesdec256kl.c
new file mode 100644
index 00000000000..70b2c6357fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/keylocker-aesdec256kl.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mkl -O2" } */
+/* { dg-final { scan-assembler "movdqa\[ \\t\]+\[^\n\]*k2\[^\n\r]*%xmm0" } } */
+/* { dg-final { scan-assembler "aesdec256kl\[ \\t\]+\[^\n\]*h1\[^\n\r]*%xmm0" } } */
+/* { dg-final { scan-assembler "sete" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm0\[^\n\r]*k1" } } */
+
+#include <immintrin.h>
+
+__m128i k1, k2;
+const char h1[48];
+
+unsigned char
+test_keylocker_3 (void)
+{
+ return _mm_aesdec256kl_u8 (&k1, k2, h1);
+}
diff --git a/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide128kl.c b/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide128kl.c
new file mode 100644
index 00000000000..b5a05cfa404
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide128kl.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-mwidekl -O2" } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata(\\(%rip\\))?\[^\n\r]*%xmm0" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+16(\\(%rip\\))?\[^\n\r]*%xmm1" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+32(\\(%rip\\))?\[^\n\r]*%xmm2" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+48(\\(%rip\\))?\[^\n\r]*%xmm3" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+64(\\(%rip\\))?\[^\n\r]*%xmm4" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+80(\\(%rip\\))?\[^\n\r]*%xmm5" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+96(\\(%rip\\))?\[^\n\r]*%xmm6" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+112(\\(%rip\\))?\[^\n\r]*%xmm7" } } */
+/* { dg-final { scan-assembler "aesdecwide128kl\[ \\t\]+\[^\n\]*h1" } } */
+/* { dg-final { scan-assembler "sete" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm0\[^\n\r]*idata(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm1\[^\n\r]*idata\\+16(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm2\[^\n\r]*idata\\+32(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm3\[^\n\r]*idata\\+48(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm4\[^\n\r]*idata\\+64(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm5\[^\n\r]*idata\\+80(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm6\[^\n\r]*idata\\+96(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm7\[^\n\r]*idata\\+112(\\(%rip\\))?" } } */
+
+#include <immintrin.h>
+
+const char h1[48];
+const __m128i idata[8];
+__m128i odata[8];
+
+unsigned char
+test_keylocker_5 (void)
+{
+ return _mm_aesdecwide128kl_u8 (odata, idata, h1);
+}
diff --git a/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide256kl.c b/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide256kl.c
new file mode 100644
index 00000000000..1c3f9de48a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/keylocker-aesdecwide256kl.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-mwidekl -O2" } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata(\\(%rip\\))?\[^\n\r]*%xmm0" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+16(\\(%rip\\))?\[^\n\r]*%xmm1" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+32(\\(%rip\\))?\[^\n\r]*%xmm2" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+48(\\(%rip\\))?\[^\n\r]*%xmm3" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+64(\\(%rip\\))?\[^\n\r]*%xmm4" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+80(\\(%rip\\))?\[^\n\r]*%xmm5" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+96(\\(%rip\\))?\[^\n\r]*%xmm6" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+112(\\(%rip\\))?\[^\n\r]*%xmm7" } } */
+/* { dg-final { scan-assembler "aesdecwide256kl\[ \\t\]+\[^\n\]*h1" } } */
+/* { dg-final { scan-assembler "sete" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm0\[^\n\r]*idata(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm1\[^\n\r]*idata\\+16(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm2\[^\n\r]*idata\\+32(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm3\[^\n\r]*idata\\+48(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm4\[^\n\r]*idata\\+64(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm5\[^\n\r]*idata\\+80(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm6\[^\n\r]*idata\\+96(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm7\[^\n\r]*idata\\+112(\\(%rip\\))?" } } */
+
+#include <immintrin.h>
+
+const char h1[48];
+const __m128i idata[8];
+__m128i odata[8];
+
+unsigned char
+test_keylocker_6 (void)
+{
+ return _mm_aesdecwide256kl_u8 (odata, idata, h1);
+}
diff --git a/gcc/testsuite/gcc.target/i386/keylocker-aesenc128kl.c b/gcc/testsuite/gcc.target/i386/keylocker-aesenc128kl.c
new file mode 100644
index 00000000000..c7bf743015e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/keylocker-aesenc128kl.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mkl -O2" } */
+/* { dg-final { scan-assembler "movdqa\[ \\t\]+\[^\n\]*k2\[^\n\r]*%xmm0" } } */
+/* { dg-final { scan-assembler "aesenc128kl\[ \\t\]+\[^\n\]*h1\[^\n\r]*%xmm0" } } */
+/* { dg-final { scan-assembler "sete" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm0\[^\n\r]*k1" } } */
+
+#include <immintrin.h>
+
+__m128i k1, k2;
+const char h1[48];
+
+unsigned char
+test_keylocker_2 (void)
+{
+ return _mm_aesenc128kl_u8 (&k1, k2, h1);
+}
diff --git a/gcc/testsuite/gcc.target/i386/keylocker-aesencwide128kl.c b/gcc/testsuite/gcc.target/i386/keylocker-aesencwide128kl.c
new file mode 100644
index 00000000000..f7b90f5e964
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/keylocker-aesencwide128kl.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-mwidekl -O2" } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata(\\(%rip\\))?\[^\n\r]*%xmm0" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+16(\\(%rip\\))?\[^\n\r]*%xmm1" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+32(\\(%rip\\))?\[^\n\r]*%xmm2" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+48(\\(%rip\\))?\[^\n\r]*%xmm3" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+64(\\(%rip\\))?\[^\n\r]*%xmm4" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+80(\\(%rip\\))?\[^\n\r]*%xmm5" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+96(\\(%rip\\))?\[^\n\r]*%xmm6" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+112(\\(%rip\\))?\[^\n\r]*%xmm7" } } */
+/* { dg-final { scan-assembler "aesencwide128kl\[ \\t\]+\[^\n\]*h1(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "sete" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm0\[^\n\r]*idata(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm1\[^\n\r]*idata\\+16(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm2\[^\n\r]*idata\\+32(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm3\[^\n\r]*idata\\+48(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm4\[^\n\r]*idata\\+64(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm5\[^\n\r]*idata\\+80(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm6\[^\n\r]*idata\\+96(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm7\[^\n\r]*idata\\+112(\\(%rip\\))?" } } */
+
+#include <immintrin.h>
+
+const char h1[48];
+const __m128i idata[8];
+__m128i odata[8];
+
+unsigned char
+test_keylocker_7 (void)
+{
+ return _mm_aesencwide128kl_u8 (odata, idata, h1);
+}
diff --git a/gcc/testsuite/gcc.target/i386/keylocker-aesencwide256kl.c b/gcc/testsuite/gcc.target/i386/keylocker-aesencwide256kl.c
new file mode 100644
index 00000000000..140e2e81e44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/keylocker-aesencwide256kl.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-mwidekl -O2" } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata(\\(%rip\\))?\[^\n\r]*%xmm0" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+16(\\(%rip\\))?\[^\n\r]*%xmm1" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+32(\\(%rip\\))?\[^\n\r]*%xmm2" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+48(\\(%rip\\))?\[^\n\r]*%xmm3" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+64(\\(%rip\\))?\[^\n\r]*%xmm4" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+80(\\(%rip\\))?\[^\n\r]*%xmm5" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+96(\\(%rip\\))?\[^\n\r]*%xmm6" } } */
+/* { dg-final { scan-assembler "movdqu\[ \\t\]+\[^\n\]*idata\\+112(\\(%rip\\))?\[^\n\r]*%xmm7" } } */
+/* { dg-final { scan-assembler "aesencwide256kl\[ \\t\]+\[^\n\]*h1(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "sete" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm0\[^\n\r]*idata(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm1\[^\n\r]*idata\\+16(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm2\[^\n\r]*idata\\+32(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm3\[^\n\r]*idata\\+48(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm4\[^\n\r]*idata\\+64(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm5\[^\n\r]*idata\\+80(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm6\[^\n\r]*idata\\+96(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm7\[^\n\r]*idata\\+112(\\(%rip\\))?" } } */
+
+#include <immintrin.h>
+
+const char h1[48];
+const __m128i idata[8];
+__m128i odata[8];
+
+unsigned char
+test_keylocker_8 (void)
+{
+ return _mm_aesencwide256kl_u8 (odata, idata, h1);
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/keylocker-encodekey128.c b/gcc/testsuite/gcc.target/i386/keylocker-encodekey128.c
new file mode 100644
index 00000000000..13b58df0f07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/keylocker-encodekey128.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-mkl -O2" } */
+/* { dg-final { scan-assembler "movdqa\[ \\t\]+\[^\n\]*k1(\\(%rip\\))?\[^\n\r]*%xmm0" } } */
+/* { dg-final { scan-assembler "movl\[ \\t\]+\[^\n\]*ctrl(\\(%rip\\))?\[^\n\r]*%eax" } } */
+/* { dg-final { scan-assembler "encodekey128\[ \\t\]+\[^\n\]*%eax\[^\n\r]*%eax" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm0\[^\n\r]*h2(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm1\[^\n\r]*h2\\+16(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm2\[^\n\r]*h2\\+32(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqa|movaps)\[ \\t\]+\[^\n\]*%xmm6\[^\n\r]*k2(\\(%rip\\))?" } } */
+
+#include <immintrin.h>
+
+unsigned int ctrl;
+char h2[48];
+__m128i k1, k2;
+
+unsigned int
+test_keylocker_9 (void)
+{
+ unsigned int ret;
+
+ ret = _mm_encodekey128_u32 (ctrl, k1, h2);
+
+ if (ret)
+ k2 = (__m128i){0};
+
+ return ret;
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/keylocker-encodekey256.c b/gcc/testsuite/gcc.target/i386/keylocker-encodekey256.c
new file mode 100644
index 00000000000..1a522ea9d4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/keylocker-encodekey256.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-mkl -O2" } */
+/* { dg-final { scan-assembler "movdqa\[ \\t\]+\[^\n\]*k1(\\(%rip\\))?\[^\n\r]*%xmm0" } } */
+/* { dg-final { scan-assembler "movdqa\[ \\t\]+\[^\n\]*k2(\\(%rip\\))?\[^\n\r]*%xmm1" } } */
+/* { dg-final { scan-assembler "movl\[ \\t\]+\[^\n\]*ctrl(\\(%rip\\))?\[^\n\r]*%eax" } } */
+/* { dg-final { scan-assembler "encodekey256\[ \\t\]+\[^\n\]*%eax\[^\n\r]*%eax" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm0\[^\n\r]*h2(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm1\[^\n\r]*h2\\+16(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm2\[^\n\r]*h2\\+32(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqu|movups)\[ \\t\]+\[^\n\]*%xmm3\[^\n\r]*h2\\+48(\\(%rip\\))?" } } */
+/* { dg-final { scan-assembler "(?:movdqa|movaps)\[ \\t\]+\[^\n\]*%xmm6\[^\n\r]*k3(\\(%rip\\))?" } } */
+
+#include <immintrin.h>
+
+unsigned int ctrl;
+char h2[48];
+__m128i k1, k2, k3;
+
+unsigned int
+test_keylocker_10 (void)
+{
+ unsigned int ret;
+ ret = _mm_encodekey256_u32 (ctrl, k1, k2, h2);
+
+ if (ret)
+ k3 = (__m128i){0};
+
+ return ret;
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/keylocker-loadiwkey.c b/gcc/testsuite/gcc.target/i386/keylocker-loadiwkey.c
new file mode 100644
index 00000000000..cc0f2e02150
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/keylocker-loadiwkey.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mkl -O2" } */
+/* { dg-final { scan-assembler "movl\[ \\t\]+\[^\n\]*ctrl(\\(%rip\\))?\[^\n\r]*%eax" } } */
+/* { dg-final { scan-assembler "movdqa\[ \\t\]+\[^\n\]*k2(\\(%rip\\))?\[^\n\r]*%xmm1" } } */
+/* { dg-final { scan-assembler "movdqa\[ \\t\]+\[^\n\]*k3(\\(%rip\\))?\[^\n\r]*%xmm2" } } */
+/* { dg-final { scan-assembler "movdqa\[ \\t\]+\[^\n\]*k1(\\(%rip\\))?\[^\n\r]*%xmm0" } } */
+/* { dg-final { scan-assembler "loadiwkey\[ \\t\]+\[^\n\]*%xmm1\[^\n\r]*%xmm2" } } */
+
+#include <immintrin.h>
+
+unsigned int ctrl;
+__m128i k1, k2, k3;
+
+void
+test_keylocker_11 (void)
+{
+ _mm_loadiwkey (ctrl, k1, k2, k3);
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c
index b1690d7204f..7494a40fe4e 100644
--- a/gcc/testsuite/gcc.target/i386/sse-12.c
+++ b/gcc/testsuite/gcc.target/i386/sse-12.c
@@ -3,7 +3,7 @@
popcntintrin.h gfniintrin.h and mm_malloc.h are usable
with -O -std=c89 -pedantic-errors. */
/* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mkl -mwidekl" } */
#include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
index 3a6404707c4..9eec8afc775 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mkl -mwidekl" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c
index edaa2aa8ad4..5b819d1197a 100644
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mkl -mwidekl" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c
index 7364b2ff337..df795f135c9 100644
--- a/gcc/testsuite/gcc.target/i386/sse-22.c
+++ b/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -102,7 +102,7 @@
#ifndef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,kl,widekl")
#endif
/* Following intrinsics require immediate arguments. They
@@ -219,7 +219,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
/* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */
#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk")
+#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,kl,widekl")
#endif
#include <immintrin.h>
test_1 (_cvtss_sh, unsigned short, float, 1)
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
index eaadebef187..0ad4ee5f94f 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -697,6 +697,6 @@
#define __builtin_ia32_vpclmulqdq_v2di(A, B, C) __builtin_ia32_vpclmulqdq_v2di(A, B, 1)
#define __builtin_ia32_vpclmulqdq_v8di(A, B, C) __builtin_ia32_vpclmulqdq_v8di(A, B, 1)
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,kl,widekl")
#include <x86intrin.h>
--
2.25.1
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2020-09-21 5:30 Enable GCC support for Intel Key Locker extension Hongyu Wang
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