From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x22e.google.com (mail-oi1-x22e.google.com [IPv6:2607:f8b0:4864:20::22e]) by sourceware.org (Postfix) with ESMTPS id 3D9873856267 for ; Fri, 6 May 2022 08:50:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3D9873856267 Received: by mail-oi1-x22e.google.com with SMTP id m11so6839242oib.11 for ; Fri, 06 May 2022 01:50:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=jm4hx/k35HOT4n2JyK8xvI2hGCGPaWPB3UV5m1eZurM=; b=g1v/6CSbrfa0dpvnP22zGIl1R4RrG1Bw0Evn6BaKcqgr2LZrcVloyb3y0LaJIZdjxt aScByXKh0ELhSM1cL57iBK5fVFMVNP/cNYbTew4dj8HtGEg937RQMuY0IX5ESOuxnFbK GN7OEVPGyyfzFJ34gWFjjVV9flXIKAo/ZLnIOvoYldFjEtIBIbrKukZW0aAge3sIhXX3 PB68FVTL6TPJ4TC1DsQVQJdFLWDebxDj/b0+g0LSYcp+uBWwJdSlutwQK5DdOgZ26JqP qXfKB515WIepL5f1SWp6oN7AhcRjjCC2AJ04q/4553G+ro9oYUDNt3p0xLFbRZvfBzQw HuyA== X-Gm-Message-State: AOAM533P7Iz3fxqCAfYX07FPQ40OyABHjc3EPsNoNms1pIG2EE3lZiWM I6FGDRN+rxpZMObOSCp3uZXAJkTPFdQ5rMF0XvcS1YuqDWnnJw== X-Google-Smtp-Source: ABdhPJyqJYKWWLMuDr6FsD4rTih5NvKGymF0lID55Rqk/eZVDEgHLyvtH44GZMajamiXPFPB5oEwvPiZco+8ffR+uoU= X-Received: by 2002:aca:4154:0:b0:322:7a9c:7daa with SMTP id o81-20020aca4154000000b003227a9c7daamr4292562oia.52.1651827003417; Fri, 06 May 2022 01:50:03 -0700 (PDT) MIME-Version: 1.0 References: <20220506080056.84313-1-haochen.jiang@intel.com> In-Reply-To: <20220506080056.84313-1-haochen.jiang@intel.com> From: Hongyu Wang Date: Fri, 6 May 2022 16:49:53 +0800 Message-ID: Subject: Re: [PATCH] [i386]Add combine splitter to transform pxor/pcmpeqb/pmovmskb/cmp 0xffff to ptest. To: Haochen Jiang Cc: GCC Patches , Hongtao Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 May 2022 08:50:06 -0000 > +(define_split > + [(set (reg:CCZ FLAGS_REG) > + (compare:CCZ (unspec:SI > + [(eq:VI1_AVX2 > + (match_operand:VI1_AVX2 0 "vector_operand") > + (match_operand:VI1_AVX2 1 "const0_operand"))] > + UNSPEC_MOVMSK) > + (match_operand 2 "const_int_operand")))] > + "TARGET_SSE4_1 && ix86_match_ccmode (insn, CCmode) It looks like set_src and set_dst are all CCZmode, do we really need ix86_match_ccmode? > + && (INTVAL (operands[2]) =3D=3D (int) ())" I think (int) convert is not needed for const, and INTVAL actually returns HOST_WIDE_INT > +#include > + > +bool is_zero(__m128i x) bool is not necessary here, we can use int and drop stdbool. Haochen Jiang via Gcc-patches =E4=BA=8E2022=E5=B9= =B45=E6=9C=886=E6=97=A5=E5=91=A8=E4=BA=94 16:01=E5=86=99=E9=81=93=EF=BC=9A > > Hi all, > > This patch aims to add a combine splitter to transform pxor/pcmpeqb/pmovm= skb/cmp 0xffff to ptest. > > Regtested on x86_64-pc-linux-gnu. Ok for trunk? > > BRs, > Haochen > > gcc/ChangeLog: > > PR target/104371 > * config/i386/sse.md: Add new define_mode_attr and define_split. > > gcc/testsuite/ChangeLog: > > PR target/104371 > * gcc.target/i386/pr104371-1.c: New test. > * gcc.target/i386/pr104371-2.c: Ditto. > --- > gcc/config/i386/sse.md | 19 +++++++++++++++++++ > gcc/testsuite/gcc.target/i386/pr104371-1.c | 14 ++++++++++++++ > gcc/testsuite/gcc.target/i386/pr104371-2.c | 14 ++++++++++++++ > 3 files changed, 47 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/i386/pr104371-1.c > create mode 100755 gcc/testsuite/gcc.target/i386/pr104371-2.c > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 7b791def542..71afda73c8f 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -20083,6 +20083,25 @@ > (set_attr "prefix" "maybe_vex") > (set_attr "mode" "SI")]) > > +;; Optimize pxor/pcmpeqb/pmovmskb/cmp 0xffff to ptest. > +(define_mode_attr vi1avx2const > + [(V32QI "0xffffffff") (V16QI "0xffff")]) > + > +(define_split > + [(set (reg:CCZ FLAGS_REG) > + (compare:CCZ (unspec:SI > + [(eq:VI1_AVX2 > + (match_operand:VI1_AVX2 0 "vector_operand") > + (match_operand:VI1_AVX2 1 "const0_operand"))] > + UNSPEC_MOVMSK) > + (match_operand 2 "const_int_operand")))] > + "TARGET_SSE4_1 && ix86_match_ccmode (insn, CCmode) > + && (INTVAL (operands[2]) =3D=3D (int) ())" > + [(set (reg:CC FLAGS_REG) > + (unspec:CC [(match_dup 0) > + (match_dup 0)] > + UNSPEC_PTEST))]) > + > (define_expand "sse2_maskmovdqu" > [(set (match_operand:V16QI 0 "memory_operand") > (unspec:V16QI [(match_operand:V16QI 1 "register_operand") > diff --git a/gcc/testsuite/gcc.target/i386/pr104371-1.c b/gcc/testsuite/g= cc.target/i386/pr104371-1.c > new file mode 100644 > index 00000000000..df7c0b074e3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr104371-1.c > @@ -0,0 +1,14 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -msse4" } */ > +/* { dg-final { scan-assembler "ptest\[ \\t\]" } } */ > +/* { dg-final { scan-assembler-not "pxor\[ \\t\]" } } */ > +/* { dg-final { scan-assembler-not "pcmpeqb\[ \\t\]" } } */ > +/* { dg-final { scan-assembler-not "pmovmskb\[ \\t\]" } } */ > + > +#include > +#include > + > +bool is_zero(__m128i x) > +{ > + return _mm_movemask_epi8(_mm_cmpeq_epi8(x, _mm_setzero_si128())) =3D= =3D 0xffff; > +} > diff --git a/gcc/testsuite/gcc.target/i386/pr104371-2.c b/gcc/testsuite/g= cc.target/i386/pr104371-2.c > new file mode 100755 > index 00000000000..f0d0afd5897 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr104371-2.c > @@ -0,0 +1,14 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mavx2" } */ > +/* { dg-final { scan-assembler "vptest\[ \\t\]" } } */ > +/* { dg-final { scan-assembler-not "vpxor\[ \\t\]" } } */ > +/* { dg-final { scan-assembler-not "vpcmpeqb\[ \\t\]" } } */ > +/* { dg-final { scan-assembler-not "vpmovmskb\[ \\t\]" } } */ > + > +#include > +#include > + > +bool is_zero256(__m256i x) > +{ > + return _mm256_movemask_epi8(_mm256_cmpeq_epi8(x, _mm256_setzero_si256(= ))) =3D=3D 0xffffffff; > +} > -- > 2.18.1 >