From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ot1-x333.google.com (mail-ot1-x333.google.com [IPv6:2607:f8b0:4864:20::333]) by sourceware.org (Postfix) with ESMTPS id 9BC78385842A for ; Mon, 20 Nov 2023 16:58:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9BC78385842A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=beagleboard.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9BC78385842A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::333 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700499510; cv=none; b=Ql1WByBvtCSbWCHKE4LxCOZJ6HLZAlUnRfOstOtiVMA5Bu7VWfJatLWLdRnbhapUQcyVTYgGb356KbxaPgnaHpzzc4Rn06kte/B1FXU3JnzDQC/cEp7ZdqVl98SoSpNrwPIf+a5Ael7WdaUZWdXDRnV75vRF+508mTsdSDHLD04= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700499510; c=relaxed/simple; bh=SOL2t06IgbgdbHubsb1eWP4IjwFuUvxQ0Z/lCra468Y=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=MNoY7lrG4N20/sFeqWItw7jYhgikttwF8V0al7wP1x30iXV3iWCXXkpk2Xeoe94Bu5KcRdZZR5/5icooPHh9Nmk0fBivo3+FNc0j0/5bD5Atxq3HNd9pJgaqccGqGZp7L37cS/qMqPLkzARnDgoyHIm+YjCu7u3E5HVZGT7GO1c= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ot1-x333.google.com with SMTP id 46e09a7af769-6cf65093780so2665154a34.0 for ; Mon, 20 Nov 2023 08:58:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail-com.20230601.gappssmtp.com; s=20230601; t=1700499507; x=1701104307; darn=gcc.gnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Lw7IEZOqtdI9YYYatrn3CokD6tFc3CnoLNnSk4/MWjU=; b=J8963CsA8fSWMv6ntJcWUFwm9Pr2+z+5+aWB8VZZT4qvCVkS0w5xqTv5JgShv8cr+D k3rS8NR+BBBSmeJFAwhwcK5Jcn41mUnyl1CxbKVZRcGWLDyT2+2+KIg2x7ENJjcW9bs3 nhsZ5Znf2WFtjEKbokGs1p8Ezgu7EhN9xLSdh/W7pH6wrFn+nKCbpQ2zKl7mAbVHc6iH 4dZz/MiV4ZUuDJTxfwE7jFub5W0mKUGGeG+ZaNiFaaDjyZXhlbIuaCCKxOFiSqZQ92Pt P32yHmIvwZ1LSBZ3Z5AYXMPCHNb+fdRztBMIjTS4PtmhasC1v9RAJUL2GXV/WH0fqWsr VFZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700499507; x=1701104307; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Lw7IEZOqtdI9YYYatrn3CokD6tFc3CnoLNnSk4/MWjU=; b=SoTBjlIpxkN4N/uwHDpAH/XRUa6RuIdtSAM7hayTdk6sjfWORr4ZD7vbTWIX68hoUj dttEeYEKWRXWpFEB5lv4+AuBlYfrjbGj715F3mVbALdmb7IBz2YbPclQ3t9RsmAg2zGr VWLuECwrAEp3DbCQpBuYriSZnQqy7UacOwaRzeSkZaVqSgcLgH9e8k+I9N7+d2tgn2br bNou58ZbeoNYSkczmQUN7R9qiZEy37w9bOOgfFx7k6YVlY3+DTC8vcymnLTcOvlyXLGR 576MhN63f9AqG5o0aQ33smDzTxEXqOhyL5YkIsAvkaN4V4jO0L9Ao1HPDp6uncYxGGOL 0nDg== X-Gm-Message-State: AOJu0YyyArfTJgAcg7/hzYF2sbB+VVmItwvO+Do5ju0nqtbj/xk+NUi2 yj3uH08iMfOH0ytQUN7BjfM1VMNcxBxxti/Uk+U= X-Google-Smtp-Source: AGHT+IGmwFNzhT7o+25zj4NehSurmehRHTUt7UqjMtLS0SGbMGrzMuiPF1wqY0BjTQbKUcMJgvfPWRaTBpV4C162gTQ= X-Received: by 2002:a05:6871:5388:b0:1e9:8ab9:e20 with SMTP id hy8-20020a056871538800b001e98ab90e20mr8960304oac.58.1700499506794; Mon, 20 Nov 2023 08:58:26 -0800 (PST) MIME-Version: 1.0 References: <086123810F5FEA3C+202311171939484236058@rivai.ai> <534975f1-c062-49d5-a9e8-794260a0aba3@gmail.com> <8A23593956C5AA11+202311201104070109787@rivai.ai> In-Reply-To: <8A23593956C5AA11+202311201104070109787@rivai.ai> From: Jason Kridner Date: Mon, 20 Nov 2023 11:58:16 -0500 Message-ID: Subject: Re: Re: RISC-V: Support XTheadVector extensions To: "juzhe.zhong@rivai.ai" Cc: Drew Fustini , "Kito.cheng" , Robert Nelson , Robin Dapp , "cooper.joshua" , gcc-patches , jeffreyalaw , "kito.cheng" , "philipp.tomsich" Content-Type: multipart/alternative; boundary="0000000000000b166c060a986591" X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,GIT_PATCH_0,HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_KAM_HTML_FONT_INVALID,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000000b166c060a986591 Content-Type: text/plain; charset="UTF-8" Adding Drew and Robert. On Sun, Nov 19, 2023 at 10:04 PM juzhe.zhong@rivai.ai wrote: > As kito's suggestions. I just have a quick try. > > This patch should does following things: > > 1. Remove all new API that RVV1.0 doesn't have. E.g. vlb. > They should be another separate patch to be reviewed. > So the first series patch should be "Support part of theadvector API > base on current RVV1.0 API" > > 2. Here is a another approach which must work for theadvector: > > diff --git a/gcc/config/riscv/riscv-protos.h > b/gcc/config/riscv/riscv-protos.h > index ae528db1898..24b514c58df 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -646,6 +646,7 @@ extern bool th_classify_address (struct > riscv_address_info *, > extern const char *th_output_move (rtx, rtx); > extern bool th_print_operand_address (FILE *, machine_mode, rtx); > #endif > +extern void th_vector_asm_output_opcode (FILE *, const char *); > > extern bool riscv_use_divmod_expander (void); > void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int); > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 3701f41b1b3..9631a428341 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -10088,6 +10088,13 @@ extract_base_offset_in_addr (rtx mem, rtx *base, > rtx *offset) > return false; > } > > +void > +th_vector_asm_output_opcode (FILE *f, const char *ptr) > +{ > + if (ptr[0] == 'v') > + fprintf (f, "th."); > +} > + > /* Initialize the GCC target structure. */ > #undef TARGET_ASM_ALIGNED_HI_OP > #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index 6205d7533f4..be02a926028 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -1206,4 +1206,6 @@ extern void riscv_remove_unneeded_save_restore_calls > (void); > #define HAVE_POST_MODIFY_DISP TARGET_XTHEADMEMIDX > #define HAVE_PRE_MODIFY_DISP TARGET_XTHEADMEMIDX > > +#define ASM_OUTPUT_OPCODE(STREAM, PTR) th_vector_asm_output_opcode > (STREAM, PTR); > + > #endif /* ! GCC_RISCV_H */ > > It does work: > > /tmp/cc0yrKxw.s:1692: Error: unrecognized opcode `th.vsetivli > zero,8,e8,mf2,ta,ma' > /tmp/cc0yrKxw.s:1693: Error: unrecognized opcode `th.vmv.v.i v1,0' > /tmp/cc0yrKxw.s:1694: Error: unrecognized opcode `th.vse8.v v1,0(a5)' > /tmp/cc0yrKxw.s:1696: Error: unrecognized opcode `th.vse8.v v1,0(a5)' > make[2]: *** [Makefile:935: _gcov.o] Error 1 > make[2]: *** Waiting for unfinished jobs.... > /tmp/cc2KYYTs.s: Assembler messages: > /tmp/cc2KYYTs.s:1606: Error: unrecognized opcode `th.vsetivli > zero,8,e8,mf2,ta,ma' > /tmp/cc2KYYTs.s:1610: Error: unrecognized opcode `th.vle8.v v1,0(a1)' > /tmp/cc2KYYTs.s:1615: Error: unrecognized opcode `th.vse8.v v1,0(sp)' > /tmp/cc2KYYTs.s:1617: Error: unrecognized opcode `th.vle8.v v1,0(a2)' > /tmp/cc2KYYTs.s:1618: Error: unrecognized opcode `th.vse8.v v1,0(a5)' > /tmp/cc2KYYTs.s:1651: Error: unrecognized opcode `th.vsetivli > zero,8,e8,mf2,ta,ma' > /tmp/cc2KYYTs.s:1671: Error: unrecognized opcode `th.vle8.v v1,0(a4)' > /tmp/cc2KYYTs.s:1674: Error: unrecognized opcode `th.vse8.v v1,0(a0)' > /tmp/cc2KYYTs.s:2469: Error: unrecognized opcode `th.vsetivli > zero,8,e8,mf2,ta,ma' > /tmp/cc2KYYTs.s:2569: Error: unrecognized opcode `th.vsetivli > zero,8,e8,mf2,ta,ma' > /tmp/cc2KYYTs.s:2580: Error: unrecognized opcode `th.vle8.v v1,0(a2)' > /tmp/cc2KYYTs.s:2581: Error: unrecognized opcode `th.vse8.v v1,0(a5)' > /tmp/cc2KYYTs.s:2643: Error: unrecognized opcode `th.vsetivli > zero,8,e8,mf2,ta,ma' > /tmp/cc2KYYTs.s:2671: Error: unrecognized opcode `th.vsetivli > zero,8,e8,mf2,ta,ma' > /tmp/cc2KYYTs.s:3294: Error: unrecognized opcode `th.vsetivli > zero,8,e8,mf2,ta,ma' > /tmp/cc2KYYTs.s:3317: Error: unrecognized opcode `th.vle8.v v1,0(a4)' > /tmp/cc2KYYTs.s:3319: Error: unrecognized opcode `th.vse8.v v1,0(a4)' > /tmp/cc2KYYTs.s:3322: Error: unrecognized opcode `th.vle8.v v1,0(a4)' > /tmp/cc2KYYTs.s:3324: Error: unrecognized opcode `th.vse8.v v1,0(a4)' > > But we need binutils support theadvector first, otherwise, it will fail > during building. > > 3. Add theadvector gating on target-support.exp. We don't want to run > theadvector test > when we don't enable theadvector. > > Thanks. > > ------------------------------ > juzhe.zhong@rivai.ai > > > *From:* Kito Cheng > *Date:* 2023-11-18 18:32 > *To:* Philipp Tomsich > *CC:* Jeff Law ; juzhe.zhong@rivai.ai; gcc-patches > ; kito.cheng ; > cooper.joshua ; Robin Dapp > ; jkridner > *Subject:* Re: RISC-V: Support XTheadVector extensions > I guess it would be worth to state my thought publicly: > > I *support* adding the T-head vector (a.k.a. vector 0.7) to upstream > GCC since T-Head vector already ships a large enough number of boards, > also it's not really T-head's problem as Palmer described in another > mail. > > My biggest concern before is T-head folks didn't involved into > community work too much, so accept that definitely will increasing > work for maintainers, however I saw T-head folks is trying to > contribute stuffs to upstream now, so may not a concern now, also I > believe accept this patch will encourage they work more on upstream > together, which is benefit to each other. > > Back to the one of the biggest issues for the patch set: GCC 14 or GCC > 15. My general thought is it may be OK if it's less invasive enough, > then should be OK for GCC 14, but I don't have a strong opinion, since > as you know I am not the main developer of the vector part, so I will > let Ju-Zhe make the final decision, because he is the one who > contributes most things to RISC-V vector gcc support. > > > --0000000000000b166c060a986591--