From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by sourceware.org (Postfix) with ESMTPS id 1D5043858D1E for ; Fri, 10 Nov 2023 09:00:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1D5043858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1D5043858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::1034 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699606857; cv=none; b=J6K2566LgX0RwmSDkpwvEjREOU5IcU5E7j4NhZ+A0EcxgIbx2MI8t6B4l3SJvmJZXTCwuRA5/JRAI1leuGPJ1s0Z6Hl+f9rI8ihFuWCCGG4uv8wGUWxqLVqN/IzK9b5T3ohzCwtJa3bXEBFfGsuLz4lLkCC8HY+yHXosYnQD8EI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699606857; c=relaxed/simple; bh=G9VX6cZQcW5l2+X+d/rDgUSeD+T7V0Rji4hGAgABPNo=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=wh0qXHbcNx8mCLBORu9MbFRwXVbdtvmz8Tj2gOHDpARQrlIn0Yi854fuAKR3q557vb1boQvaYo+RLvKTqJ5joDEua2QOtewP0zwo++7FeGuu/6tqk+uaPgpOVk1Dy+fELa2Oc5SyhDFRKsKqwCw9CaTOgRaPhXoh8qJSPtXQTLo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-28120aa1c24so1550821a91.0 for ; Fri, 10 Nov 2023 01:00:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1699606853; x=1700211653; darn=gcc.gnu.org; h=to:subject:message-id:date:from:mime-version:from:to:cc:subject :date:message-id:reply-to; bh=3VMd+FCTQrKY4QRgMg/5LoFR8ZXTGfgv+QN4XJnADbM=; b=JYnW5yn8QTo4jfD/TXuX0CyMsw7yh263C3nByMnB5eIfr5w/C05VCaw/wHXzJPbAfp ArMjR8imz9Mg1CfQUR1O1PfCdWR0eHNplAptRZOQuir4fhlidtbuiE1jKFWdhpX9uFPF s0cvJmH6LrURzW7Y1SLUlVvFGlBJ6anj+lYndTPtrgcjkGpvsDBuV1hEatIn84TCXf7t 6MXYIqk/yPlOC9LXjv1qOhCsLYh1OFccGQvnB4bUjLPkHeRbtI40JL1o/J1J7fFnPYDT tP/yRwGZSZbqBzU3v8beRO1eNLxSguULuCdfzyGugfWAr8hyTJf+Nz0ePrJZiM+R+tf6 jqDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699606853; x=1700211653; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=3VMd+FCTQrKY4QRgMg/5LoFR8ZXTGfgv+QN4XJnADbM=; b=WkY/wwu48viu2NfBSuMW/thYX6fR8UN2mlZtt0t1PnO6y5VMVyGCi5rXgG/yjSojoj QIroj4mZMdjBPK+ym4h61bqQHcghzvU7w/Tbe+T+l79Gt/1+I9fdf2B+4rIfLbSI5S27 oxXvK8wjABl5JD4TVyaKVs8miA+wKRUeyqpuD099tfs/QIhSynTOxziVqVLsS76TW7ph PjEqVgg52bmU4WtEAqw9jfuzVa4DCEzBA8DoBxSwygo+MeIovOZgqxcdzBmLR2piMij/ I+nApiFJqwNezl7Dz6azhYAz3SMWynxvNSoXBuuY6/uMlOVY/wm4tGs/O5k5PfLdyy7x t4Zw== X-Gm-Message-State: AOJu0YwMevSGnCH3/9T10PfVuEWZF2ELhHmhr8a3M2JybIzL8XnZAQuE +SV7G+jwg3kPleoTLDAg2ZhciJgwK0p79GTEA2YOHPgcxcw= X-Google-Smtp-Source: AGHT+IHV4+PG7eDv1z3Iu3hnpf46I3wlY5BIKsqyH4N78TteHbkCCIxB0iqt0gzuhvl8Jl7+jl7w2uogs+Oyr5KkmOY= X-Received: by 2002:a17:90a:1a4a:b0:27d:58a8:fa7f with SMTP id 10-20020a17090a1a4a00b0027d58a8fa7fmr4141171pjl.37.1699606852713; Fri, 10 Nov 2023 01:00:52 -0800 (PST) MIME-Version: 1.0 From: KuanLin Chen Date: Fri, 10 Nov 2023 17:00:41 +0800 Message-ID: Subject: [RFC][V2] RISC-V: Support -mcmodel=large. To: gcc-patches@gcc.gnu.org, jeffreyalaw@gmail.com, Kito Cheng Content-Type: multipart/mixed; boundary="000000000000b6d4b90609c88ec5" X-Spam-Status: No, score=0.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,HTML_MESSAGE,KAM_SHORT,KAM_STOCKGEN,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000b6d4b90609c88ec5 Content-Type: multipart/alternative; boundary="000000000000b6d4b60609c88ec3" --000000000000b6d4b60609c88ec3 Content-Type: text/plain; charset="UTF-8" gcc/ChangeLog: * gcc/config/riscv/predicates.md(move_operand): Check SYMBOL_REF and LABEL_REF type. (call_insn_operand): Support for CM_Large. (pcrel_symbol_operand): New. * gcc/config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add builtin_define "__riscv_cmodel_large". * gcc/config/riscv/riscv-opts.h (riscv_code_model): Define CM_LARGE. * gcc/config/riscv/riscv-protos.h (riscv_symbol_type): Define SYMBOL_FORCE_TO_MEM. * gcc/config/riscv/riscv.cc (riscv_classify_symbol) Support CM_LARGE model. (riscv_symbol_insns) Add SYMBOL_FORCE_TO_MEM. (riscv_cannot_force_const_mem): Ditto. (riscv_split_symbol): Ditto. (riscv_force_address): Check pseudo reg available before force_reg. (riscv_can_use_per_function_literal_pools_p): New. (riscv_elf_select_rtx_section): Literal pool stays with the function. (riscv_output_mi_thunk): Add riscv_in_thunk_func. (riscv_option_override): Support CM_LARGE model. (riscv_function_ok_for_sibcall): Disable sibcalls in CM_LARGE model. * gcc/config/riscv/riscv.h (ASM_OUTPUT_POOL_EPILOGUE): Hookfg * gcc/config/riscv/riscv.md (unspec): Define UNSPEC_FORCE_FOR_MEM. (*large_load_address"): New. * gcc/config/riscv/riscv.opt (code_model): New. gcc/testsuite/ChangeLog: * gcc/testsuite/gcc.target/riscv/large-model.c: New test. Hi Jeff, Thanks for your review. > return (absolute_symbolic_oeprand (op, mode)> || plt_symbolic_operand (op, mode) > || register_operand (op, mode); Sorry for the unformatted indet. Fixed it at the V2 patch. >> @@ -1972,7 +1992,19 @@ static rtx >> riscv_force_address (rtx x, machine_mode mode) >> { >> if (!riscv_legitimate_address_p (mode, x, false)) >> - x = force_reg (Pmode, x); >> + { >> + if (can_create_pseudo_p ()) >> + return force_reg (Pmode, x); > Note that $ra is fixed now. So if you need a scratch register, you can > fall back to $ra. > More importantly, what are the circumstances where you can be asked to > force an address after the register allocation/reloading phase is > complete? Or does it happen within the register allocators (the latter > would be an indicator we need a secondary reload). This address forcing is from riscv_output_mi_thunk: insn = emit_call_insn (gen_sibcall (fnaddr, const0_rtx, callee_cc)). This hook is called after IRA/LRA so it cannot use pseudo registers. When compiler tries to expand 'sibcall', it calls riscv_legitimize_call_address and 'fnaddr' is not a legal call_insn_operand. Then, the address goes a long-distance trip to legitimize. Here is a example that using output thunks === class base { virtual int foo(int a); }; class derived : public virtual base { virtual int foo(int a); }; int base::foo(int a) { return a; } int derived::foo(int a) { return a; } base* make() { return new derived; } === >> riscv_in_small_data_p (const_tree x) > How does large code model impact our ability to access small data > through $gp? Aren't they independent? I thought constant pool entries may be put into the small data section. But it seems I was wrong. Removed this part at V2 patch. >> + if ((offset & 3) && riscv_can_use_per_function_literal_pools_p ()) >> + ASM_OUTPUT_ALIGN (f, 2); >> +} > So the comment implies you're aligning the section. If that were the > case, then why doesn't the function alignment come from > FUNCTION_BOUNDARY when we first start emitting the function? > Or is it the case that the comment is incorrect and you've actually got > mixed code/rodata? I forgot there is an alignment from FUNCTION_BOUNDARY. Removed this part at V2 patch. >> +(define_insn "*large_load_address" >> + [(set (match_operand:DI 0 "register_operand" "=r") >> + (mem:DI (match_operand 1 "pcrel_symbol_operand" "")))] >> + "TARGET_64BIT && riscv_cmodel == CM_LARGE" >> + "ld\t%0,%1" >> + [(set_attr "type" "load") >> + (set (attr "length") (const_int 8))]) > So it would seem like you're relying on the assembler to expand the ld? > Is there any reasonable way to expose this properly to the compiler? > I'd start by emitting the right instructions in the template. Once > that's working, then we could look to split the components into distinct > insns. > I also worry that we've got a mem->reg move instruction that is not > implemented in the standard movXX patterns. Traditionally that's been a > recipe for problems. It was certainly a requirement for reload, but I > don't know offhand if it's a hard requirement for LRA. > Can you try to merge that in with the standard movdi pattern? This is a tricky idea for loading the constant pool anchor. The idea comes from the pattern '*local_pic_load'. If removing this rtl pattern, GCC will generate 'lla a5,.LC0 + ld a0,0(a5)' to get the anchor address. But with this pattern, GCC can generate 'ld a0,.LC0'. And the code generation is easier for the linker to relax. > Overall it looks pretty good. Does Andestech have a copyright > assignment in place? Or are you contributing under the DCO rule? As Kito mentioned, Andestech and I have signed FSF copyright assignment. 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