From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe2b.google.com (mail-vs1-xe2b.google.com [IPv6:2607:f8b0:4864:20::e2b]) by sourceware.org (Postfix) with ESMTPS id 465083959C88 for ; Thu, 26 Jan 2023 19:18:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 465083959C88 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe2b.google.com with SMTP id h19so1200256vsv.13 for ; Thu, 26 Jan 2023 11:18:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=/m8I+iIKzT16TQgHpV8ynOdyfveJXHuh8ALFqppoCsY=; b=SPoIycrnd6F2udi6/oKSiNHkStkZE110t6kR3tzq2B8I1/+Mc2I7SdnU3RURYIwjl7 ivTMB5UzK1+AbIzkKomi8R53hAqFAJnM96Z4Cu0y6OknqtdKoyz3pFsK52CIsxKgptgO RGK0K5HQLBht9Bg6QSVQnefWTlvCvJE0SgyT51gcsodd3N/7BzySndBw7RxMuULbUBR2 U8T/+x8JszvMejIVJNjqAbW2fxGtGTudAaZkm89HVljwHIqt6RiGuR5pTEf3KzjzwhO6 5MJcfTPKoXXRw6B8HEjRTrSa5QzGed/DnbSxp/bp9OW7Ej1jjQrvZlx8tuxuBvZfkge1 fEwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=/m8I+iIKzT16TQgHpV8ynOdyfveJXHuh8ALFqppoCsY=; b=IOj+DgMI9bNPDBtrGWPsStus3L26nRclVZVjmxufTS1p1Dsu4MpfdYxi0qsLSSoFHn RTgel5EW/fabvY+nnYs3yrHQ+sOQB/qzdUmX25KDDrj52zEiBY36crEnrR7S+piw4LG2 V94dPP/gBL4r9+ZuWsWogRQaPbEaGdc3kj+iXBIN4PUBd9Gx2TEWxKkXwufhCjcn9Bac r+uTTBn/v+LhYhOGEnPPYvuPA+EBnRzb2VmNNat6ebZiuSv2pTqdSdv3lwdx4xHNrPBR D7B9K+1u8RWl2gDewVG4NyVzh3Q1YrJhvMrp7ue0eaOrdnBK5oRiF4Ac7SYu+ZPaQN5m oMuA== X-Gm-Message-State: AO0yUKXjt26DLleZG/HpkXwjp8QXivGQz7rMzs9CxjrkaEMRVxDSKClN R7gH1jFrwFfD94syHDUT58iRWBgrfwycHz+ViKtAzf9PhXs= X-Google-Smtp-Source: AK7set+Ar2/pdr+6T8puZS5EVW+e3r4IFiJrTb7JHi++tMBtPiF3sEt2/C3nW6xeVdH0OSIL4+5wKlbJla5BjHjA27I= X-Received: by 2002:a67:fe13:0:b0:3e9:a641:7acb with SMTP id l19-20020a67fe13000000b003e9a6417acbmr936830vsr.30.1674760679340; Thu, 26 Jan 2023 11:17:59 -0800 (PST) MIME-Version: 1.0 References: <20230109234026.161632-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230109234026.161632-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Fri, 27 Jan 2023 03:17:48 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add the rest testcases of AVL=REG support To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com Content-Type: multipart/alternative; boundary="00000000000060413d05f32f9ba7" X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SCC_10_SHORT_WORD_LINES,SCC_20_SHORT_WORD_LINES,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000060413d05f32f9ba7 Content-Type: text/plain; charset="UTF-8" committed, thanks. On Tue, Jan 10, 2023 at 7:41 AM wrote: > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/vsetvl/avl_single-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-10.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-11.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-12.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-13.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-14.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-15.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-16.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-17.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-18.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-19.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-7.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-70.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-71.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-8.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-9.c: New test. > > --- > .../riscv/rvv/vsetvl/avl_single-1.c | 17 ++++++ > .../riscv/rvv/vsetvl/avl_single-10.c | 21 +++++++ > .../riscv/rvv/vsetvl/avl_single-11.c | 21 +++++++ > .../riscv/rvv/vsetvl/avl_single-12.c | 19 +++++++ > .../riscv/rvv/vsetvl/avl_single-13.c | 28 ++++++++++ > .../riscv/rvv/vsetvl/avl_single-14.c | 27 +++++++++ > .../riscv/rvv/vsetvl/avl_single-15.c | 27 +++++++++ > .../riscv/rvv/vsetvl/avl_single-16.c | 32 +++++++++++ > .../riscv/rvv/vsetvl/avl_single-17.c | 29 ++++++++++ > .../riscv/rvv/vsetvl/avl_single-18.c | 29 ++++++++++ > .../riscv/rvv/vsetvl/avl_single-19.c | 40 +++++++++++++ > .../riscv/rvv/vsetvl/avl_single-7.c | 17 ++++++ > .../riscv/rvv/vsetvl/avl_single-70.c | 41 ++++++++++++++ > .../riscv/rvv/vsetvl/avl_single-71.c | 54 ++++++++++++++++++ > .../riscv/rvv/vsetvl/avl_single-72.c | 46 +++++++++++++++ > .../riscv/rvv/vsetvl/avl_single-8.c | 18 ++++++ > .../riscv/rvv/vsetvl/avl_single-9.c | 56 +++++++++++++++++++ > 17 files changed, 522 insertions(+) > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c > new file mode 100644 > index 00000000000..84225dbe7d2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c > @@ -0,0 +1,17 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (void * restrict in, void * restrict out, int n, int vl) > +{ > + for (int i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + } > +} > + > +/* { dg-final { scan-assembler-times > {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts > "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" > no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c > new file mode 100644 > index 00000000000..f64d1c3680f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c > @@ -0,0 +1,21 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (void * restrict in, void * restrict out, int n) > +{ > + size_t vl = 39; > + for (int i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + > + vint8mf2_t v2 = __riscv_vle8_v_i8mf2 (in + i + 100, vl); > + __riscv_vse8_v_i8mf2 (out + i + 100, v2, vl); > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" > no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c > new file mode 100644 > index 00000000000..e1a8383e0db > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c > @@ -0,0 +1,21 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (void * restrict in, void * restrict out, int n) > +{ > + size_t vl = 39; > + for (int i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl); > + __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl); > + } > +} > + > +/* { dg-final { scan-assembler-times > {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts > "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" > no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c > new file mode 100644 > index 00000000000..027bc387a5e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c > @@ -0,0 +1,19 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (int8_t * restrict in, int8_t * restrict out, int n, int cond) > +{ > + if (cond == 2) { > + size_t vl = 101; > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 900, vl); > + __riscv_vse8_v_i8mf8 (out + 900, v, vl); > + vl = 102; > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + 1000, vl); > + __riscv_vse8_v_i8mf8 (out + 1000, v2, vl); > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" > no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c > new file mode 100644 > index 00000000000..faf68950ad7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c > @@ -0,0 +1,28 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (int8_t * restrict in, int8_t * restrict out, int n, int cond) > +{ > + size_t vl = 101; > + for (size_t i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl); > + __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl); > + } > + > + for (size_t i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl); > + __riscv_vse8_v_i8mf8 (out + i + 300, v, vl); > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 200, vl); > + __riscv_vse8_v_i8mf8 (out + i + 200, v2, vl); > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" > no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c > new file mode 100644 > index 00000000000..501d14c6e2d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c > @@ -0,0 +1,27 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (int8_t * restrict in, int8_t * restrict out, int n, int cond) > +{ > + size_t vl = 101; > + > + for (size_t i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl); > + __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl); > + } > + > + for (size_t i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl); > + __riscv_vse8_v_i8mf8 (out + i + 300, v, vl); > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" > no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c > new file mode 100644 > index 00000000000..501e0766c22 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c > @@ -0,0 +1,27 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (int8_t * restrict in, int8_t * restrict out, int n, int cond) > +{ > + size_t vl = 101; > + > + for (size_t i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl); > + __riscv_vse8_v_i8mf8 (out + i + 300, v, vl); > + } > + > + for (size_t i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl); > + __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl); > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" > no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c > new file mode 100644 > index 00000000000..75bed40562d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int > cond) > +{ > + size_t vl = 101; > + vbool64_t mask = *(vbool64_t*) (in + 1000000); > + for (size_t j = 0; j < m; j++){ > + for (size_t i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in + i + j + > 100, vl); > + __riscv_vse8_v_i8mf8_m (mask, out + i + j + 100, v2, vl); > + } > + > + for (size_t i = 0; i < n; i++) > + { > + vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j + > 200), vl); > + __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl); > + > + vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float > *)(in + i + j + 300), vl); > + __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2, > vl); > + } > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts > "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" > no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c > new file mode 100644 > index 00000000000..ad2b34095eb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c > @@ -0,0 +1,29 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int > cond) > +{ > + size_t vl = 101; > + vbool64_t mask = *(vbool64_t*) (in + 1000000); > + for (size_t j = 0; j < m; j++){ > + for (size_t i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + } > + > + for (size_t i = 0; i < n; i++) > + { > + vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j + > 200), vl); > + __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl); > + > + vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float > *)(in + i + j + 300), vl); > + __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2, > vl); > + } > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { > no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" > no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c > new file mode 100644 > index 00000000000..3860c6d54ff > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c > @@ -0,0 +1,29 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int > cond) > +{ > + size_t vl = 101; > + vbool64_t mask = *(vbool64_t*) (in + 1000000); > + for (size_t j = 0; j < m; j++){ > + for (size_t i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in + i + j + > 100, vl); > + __riscv_vse8_v_i8mf8_m (mask, out + i + j + 100, v2, vl); > + } > + > + for (size_t i = 0; i < n; i++) > + { > + vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j + > 200), vl); > + __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl); > + } > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts > "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" > no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c > new file mode 100644 > index 00000000000..350e1d08180 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c > @@ -0,0 +1,40 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int > cond) > +{ > + size_t vl = 101; > + vbool64_t mask = *(vbool64_t*) (in + 1000000); > + for (size_t j = 0; j < m; j++){ > + for (size_t i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + } > + > + for (size_t i = 0; i < n * n; i++) > + out[i] = out[i] * out[i]; > + for (size_t i = 0; i < n * n * n; i++) > + out[i] = out[i] + out[i]; > + for (size_t i = 0; i < n * n * n * n; i++) > + out[i] = out[i] + 2; > + for (size_t i = 0; i < n * n * n * n * n; i++) > + out[i] = out[i] * 100; > + for (size_t i = 0; i < n * n * n * n * n * n; i++) > + out[i] = out[i] - 77; > + > + for (size_t i = 0; i < n; i++) > + { > + vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j + > 200), vl); > + __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl); > + > + vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float > *)(in + i + j + 300), vl); > + __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2, > vl); > + } > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { > no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" > no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c > new file mode 100644 > index 00000000000..bd407b25d54 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c > @@ -0,0 +1,17 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (void * restrict in, void * restrict out, int n) > +{ > + register size_t vl asm ("a5"); > + for (int i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*a5,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts > "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" > no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c > new file mode 100644 > index 00000000000..89036abc9d8 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c > @@ -0,0 +1,41 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize > -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (int8_t * restrict in, int8_t * restrict out, int l, int n, int m, > size_t cond) > +{ > + size_t vl = 555; > + for (int i = 0; i < l; i++){ > + for (int j = 0; j < m; j++){ > + for (int k = 0; k < n; k++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k, vl); > + __riscv_vse8_v_i8mf8 (out + i + j + k, v, vl); > + } > + } > + } > + > + for (int i = 0; i < l; i++){ > + for (int j = 0; j < m; j++){ > + for (int k = 0; k < n; k++) > + { > + out[i+j+k+10000000] = out[i+j+k+10000000] + in[i+j+k+10000000]; > + } > + } > + } > + > + for (int i = 0; i < l; i++){ > + for (int j = 0; j < m; j++){ > + for (int k = 0; k < n; k++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k + 10000, > vl); > + v = __riscv_vle8_v_i8mf8_tu (v, in + i + j + k + 20000, vl); > + __riscv_vse8_v_i8mf8 (out + i + j + k + 10000, v, vl); > + } > + } > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" > no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c > new file mode 100644 > index 00000000000..0f780a7cb55 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c > @@ -0,0 +1,54 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize > -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (int8_t * restrict in, int8_t * restrict out, int l, int n, int m, > size_t cond) > +{ > + size_t vl = 555; > + > + if (cond) { > + for (int i = 0; i < l; i++){ > + for (int j = 0; j < m; j++){ > + for (int k = 0; k < n; k++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k, vl); > + __riscv_vse8_v_i8mf8 (out + i + j + k, v, vl); > + } > + } > + } > + } else { > + for (int i = 0; i < l; i++){ > + for (int j = 0; j < m; j++){ > + for (int k = 0; k < n; k++) > + { > + vint32mf2_t v = __riscv_vle32_v_i32mf2 ((int32_t *)(in + i + > j + k), vl); > + __riscv_vse32_v_i32mf2 ((int32_t *)(out + i + j + k), v, vl); > + } > + } > + } > + } > + > + for (int i = 0; i < l; i++){ > + for (int j = 0; j < m; j++){ > + for (int k = 0; k < n; k++) > + { > + out[i+j+k+10000000] = out[i+j+k+10000000] + in[i+j+k+10000000]; > + } > + } > + } > + > + for (int i = 0; i < l; i++){ > + for (int j = 0; j < m; j++){ > + for (int k = 0; k < n; k++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k + 10000, > vl); > + v = __riscv_vle8_v_i8mf8_tu (v, in + i + j + k + 20000, vl); > + __riscv_vse8_v_i8mf8 (out + i + j + k + 10000, v, vl); > + } > + } > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts > "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" > no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c > new file mode 100644 > index 00000000000..866370f0618 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c > @@ -0,0 +1,46 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize > -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (int8_t * restrict in, int8_t * restrict out, int l, int n, int m, > size_t cond) > +{ > + size_t vl = 555; > + > + if (cond) { > + for (int i = 0; i < l; i++){ > + for (int j = 0; j < m; j++){ > + for (int k = 0; k < n; k++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k, vl); > + __riscv_vse8_v_i8mf8 (out + i + j + k, v, vl); > + } > + } > + } > + } else { > + out[999] = out[999] * in[999]; > + } > + > + for (int i = 0; i < l; i++){ > + for (int j = 0; j < m; j++){ > + for (int k = 0; k < n; k++) > + { > + out[i+j+k+10000000] = out[i+j+k+10000000] + in[i+j+k+10000000]; > + } > + } > + } > + > + for (int i = 0; i < l; i++){ > + for (int j = 0; j < m; j++){ > + for (int k = 0; k < n; k++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k + 10000, > vl); > + v = __riscv_vle8_v_i8mf8_tu (v, in + i + j + k + 20000, vl); > + __riscv_vse8_v_i8mf8 (out + i + j + k + 10000, v, vl); > + } > + } > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts > "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" > no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c > new file mode 100644 > index 00000000000..0785af7f020 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (void * restrict in, void * restrict out, int n) > +{ > + size_t vl = 32; > + for (int i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + } > +} > + > +/* { dg-final { scan-assembler-times > {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts > "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" > no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c > new file mode 100644 > index 00000000000..0ecfb969685 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c > @@ -0,0 +1,56 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns > -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (void * restrict in, void * restrict out, int l, int n, int m) > +{ > + int vl = 32; > + for (int i = 0; i < n; i++) > + { > + vint8mf8_t v1 = __riscv_vle8_v_i8mf8 (in + i + 1, vl); > + __riscv_vse8_v_i8mf8 (out + i + 1, v1, vl); > + > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8 (in + i + 2, vl); > + __riscv_vse8_v_i8mf8 (out + i + 2, v2, vl); > + > + vint8mf8_t v3 = __riscv_vle8_v_i8mf8 (in + i + 3, vl); > + __riscv_vse8_v_i8mf8 (out + i + 3, v3, vl); > + > + vint8mf8_t v4 = __riscv_vle8_v_i8mf8 (in + i + 4, vl); > + __riscv_vse8_v_i8mf8 (out + i + 4, v4, vl); > + > + vint8mf8_t v5 = __riscv_vle8_v_i8mf8 (in + i + 5, vl); > + __riscv_vse8_v_i8mf8 (out + i + 5, v5, vl); > + > + vint8mf8_t v6 = __riscv_vle8_v_i8mf8 (in + i + 6, vl); > + __riscv_vse8_v_i8mf8 (out + i + 6, v6, vl); > + > + vint8mf8_t v7 = __riscv_vle8_v_i8mf8 (in + i + 7, vl); > + __riscv_vse8_v_i8mf8 (out + i + 7, v7, vl); > + > + vint8mf8_t v8 = __riscv_vle8_v_i8mf8 (in + i + 8, vl); > + __riscv_vse8_v_i8mf8 (out + i + 8, v8, vl); > + > + vint8mf8_t v9 = __riscv_vle8_v_i8mf8 (in + i + 9, vl); > + __riscv_vse8_v_i8mf8 (out + i + 9, v9, vl); > + > + vint8mf8_t v10 = __riscv_vle8_v_i8mf8 (in + i + 10, vl); > + __riscv_vse8_v_i8mf8 (out + i + 10, v10, vl); > + > + vint8mf8_t v11 = __riscv_vle8_v_i8mf8 (in + i + 11, vl); > + __riscv_vse8_v_i8mf8 (out + i + 11, v11, vl); > + > + vint8mf8_t v12 = __riscv_vle8_v_i8mf8 (in + i + 12, vl); > + __riscv_vse8_v_i8mf8 (out + i + 12, v12, vl); > + > + vint8mf8_t v13 = __riscv_vle8_v_i8mf8 (in + i + 13, vl); > + __riscv_vse8_v_i8mf8 (out + i + 13, v13, vl); > + > + vint8mf8_t v14 = __riscv_vle8_v_i8mf8 (in + i + 14, vl); > + __riscv_vse8_v_i8mf8 (out + i + 14, v14, vl); > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" > no-opts "-g" no-opts "-funroll-loops" } } } } */ > -- > 2.36.1 > > --00000000000060413d05f32f9ba7--