From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x929.google.com (mail-ua1-x929.google.com [IPv6:2607:f8b0:4864:20::929]) by sourceware.org (Postfix) with ESMTPS id 114F7388FB49 for ; Wed, 7 Dec 2022 14:15:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 114F7388FB49 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x929.google.com with SMTP id v21so6080198uam.1 for ; Wed, 07 Dec 2022 06:15:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=+VjRa72IM/6VXocspu6OEjdT/Piy9wV79fT8pQQTxSI=; b=GKn0tk0f2jsxo+qOL/BVlZDkIKuP8o0mlVmIxYRuuVqzdFgndbpfJJPbSNmVb7Kxs/ ZVuFzWTCTOO6x0xi5e0Cq16eS3UwY2ox7oIyuXM8+25zLQ1qK9ABZEloZnCqXq2PDk9n qRVl65vGmp00BUP9/Kn5qgqyjtLiyiV0IMs4zwAPJeHgK8Wx/aSlTOyjOxNUeq9fH969 FipTOx92+mMs+/euYyalKV+W21pzBXzct2mDX900jQnQYLgcLlelTD4D2S/++sKtYUTl /3ieFHctlC0ul6TPQm761nf2LCtJlTkecvRbIiptBlLPDQ4ot6Zfrj5hgx+sxysluIWE KTDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=+VjRa72IM/6VXocspu6OEjdT/Piy9wV79fT8pQQTxSI=; b=R0gX3IRdVoGhpEBwXkIGCK48zQyMfmm37JSxyjTQG1P/6gYBG3wwr5Gus9ef/w6+ul jO2ttUqnZumNuq0cFSaXDv0DZYs3SmHY/v+QsqKGY2inNTxMPN0uw87xVCfEqB+NqUUK VkCTPcT/ICR6Lt/lsqEmebrFK+y6XVgNBWqX2BVN8LYsvS7hXDbT13PDsfK4xm0bvGM9 Ey+MVnBJrcNmzlJUnl6ffoccebF9UI/6paGmBBRJQ+jzK4N+UJ+4rI+G6LIXhMmGceNH 62xVKLwoWMzk1VIr/0P0wFceLOtTrN5z7hNY1FUWPIo/TVyJC0EcncBPUqB8AcRytAnY XO5Q== X-Gm-Message-State: ANoB5pkiVYx9vcfZvhPSyKqTY59JLWUqW8Mf5d+cBbHATt0YlC06tCqq nwnkA/iQt8NtvABHiE9znIj0x17S7/8tFKMrPiw= X-Google-Smtp-Source: AA0mqf4PBaF7BJa/Am6WjwUrXgBJCxO25wo0cH9baZy9iTuyQPdcux1he0U39o+pp0VtOqzSFv3rU/1uNsFgwmf0vV0= X-Received: by 2002:ab0:5bdc:0:b0:415:8954:bd51 with SMTP id z28-20020ab05bdc000000b004158954bd51mr42552347uae.97.1670422543131; Wed, 07 Dec 2022 06:15:43 -0800 (PST) MIME-Version: 1.0 References: <20220810154456.101086-1-kito.cheng@sifive.com> In-Reply-To: From: Kito Cheng Date: Wed, 7 Dec 2022 22:15:31 +0800 Message-ID: Subject: Re: [PATCH v2 1/2] RISC-V: Support _Float16 type. To: "Maciej W. Rozycki" Cc: Jim Wilson , Kito Cheng , Palmer Dabbelt , andrew@sifive.com, gcc-patches@gcc.gnu.org, joseph@codesourcery.com, juzhe.zhong@rivai.ai Content-Type: multipart/alternative; boundary="0000000000004ef04e05ef3d8e04" X-Spam-Status: No, score=-6.7 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000004ef04e05ef3d8e04 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Maciej: It=E2=80=99s not intentionally, I suspect that is because I port from our i= nternal old gcc branch, will send patch to fix that later, thanks for catching this! Maciej W. Rozycki =E6=96=BC 2022=E5=B9=B412=E6=9C=885= =E6=97=A5 =E9=80=B1=E4=B8=80=EF=BC=8C21:05=E5=AF=AB=E9=81=93=EF=BC=9A > Hi Kito, > > I came across this issue while inspecting code and I have been wondering > what the reason was to downgrade current FMV.X.W and FMW.W.X instructions > to their older FMV.S.W and FMV.W.S variants here: > > On Wed, 10 Aug 2022, Kito Cheng wrote: > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > index 5a0adffb5ce..47e6110767c 100644 > > --- a/gcc/config/riscv/riscv.cc > > +++ b/gcc/config/riscv/riscv.cc > > @@ -2308,10 +2310,19 @@ riscv_output_move (rtx dest, rtx src) > > if (dest_code =3D=3D REG && GP_REG_P (REGNO (dest))) > > { > > if (src_code =3D=3D REG && FP_REG_P (REGNO (src))) > > - return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.w\t%0,%1"; > > + switch (width) > > + { > > + case 2: > > + /* Using fmv.x.s + sign-extend to emulate fmv.x.h. */ > > + return "fmv.x.s\t%0,%1;slli\t%0,%0,16;srai\t%0,%0,16"; > > + case 4: > > + return "fmv.x.s\t%0,%1"; > > + case 8: > > + return "fmv.x.d\t%0,%1"; > > + } > > and here: > > > @@ -2353,18 +2364,24 @@ riscv_output_move (rtx dest, rtx src) > > return "mv\t%0,%z1"; > > > > if (FP_REG_P (REGNO (dest))) > > - { > > - if (!dbl_p) > > - return "fmv.w.x\t%0,%z1"; > > - if (TARGET_64BIT) > > - return "fmv.d.x\t%0,%z1"; > > - /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */ > > - gcc_assert (src =3D=3D CONST0_RTX (mode)); > > - return "fcvt.d.w\t%0,x0"; > > - } > > + switch (width) > > + { > > + case 2: > > + /* High 16 bits should be all-1, otherwise HW will treated > > + as a n-bit canonical NaN, but isn't matter for > softfloat. */ > > + return "fmv.s.x\t%0,%1"; > > + case 4: > > + return "fmv.s.x\t%0,%z1"; > > + case 8: > > + if (TARGET_64BIT) > > + return "fmv.d.x\t%0,%z1"; > > + /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w = */ > > (Incorrect comment formatting here as well.) > > > + gcc_assert (src =3D=3D CONST0_RTX (mode)); > > + return "fcvt.d.w\t%0,x0"; > > + } > > Was it intentional or just an oversight in review? If intentional, I'd > expect such a change to happen on its own rather than sneaked in with a > large functional update. > > Maciej > --0000000000004ef04e05ef3d8e04--