From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x92b.google.com (mail-ua1-x92b.google.com [IPv6:2607:f8b0:4864:20::92b]) by sourceware.org (Postfix) with ESMTPS id DA0963858D33 for ; Mon, 17 Jul 2023 10:30:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DA0963858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x92b.google.com with SMTP id a1e0cc1a2514c-791c27bb91dso2932928241.0 for ; Mon, 17 Jul 2023 03:30:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689589853; x=1692181853; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=TsHDQ84uWK/AGbPSs67FFcKOVZaed1IS1p/VOOlLn8c=; b=IQoI0WRJwVGrBpbmYtZQMrcjID14Ws3GYBRBkaJOykNRlX5hUccZlm6zl4OpxtoZEe wfHbTmqSBuGhExdBOgGSyzrZ5avq5iMA1m+5Px72yXQmAKISrN5AzGLBcFKo0uhHzuUY ENotYaKACaqDZJh43Ecd0MCRUGTJXA+zsPy5sjch3STMo4TP03wcM8PbmrT2a8eyGbE3 FSkPF4x6fM2U80CC+99sYCJjPji8ncfYn/F1JC9GFwBBkRayfkj1RlPzUVxghKZPTr6P EKQUhLrtX+Ag706mYt/Ciz/TKq4DPr3thO0T/WbwEtUn4VJL50bTr82Rtz/3/Yd6DzqM mU5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689589853; x=1692181853; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TsHDQ84uWK/AGbPSs67FFcKOVZaed1IS1p/VOOlLn8c=; b=JDeF7WFjhywc4jwDB3Z+UoS7Vk9qZ4IMkaIdVggiCxq2C43PDF0+Cudl8myMV3+6yL gkEYR/iIUb5KWRwZQq/kSGZERzxN8WbDsSWzPJ/Yz9ovtkklRVEz+BFVIQLvC0ftUxeC DD7nMwgH6zVzoVTGfm41FqhG6xNKo/SlERVjE6Fbk2xizoc9a4gDrMgTmpnNnebDzT1D 7qv/WR27zjS5RB+BIuzWHjndLplmhoeNBFDekT9RsZVs3DG4NsCevrFDwrWwRchtwrNV AH/Xp64+u077CYpmurKH7TxiqYXMSKQ1GMW15oRFiMxOhGafailx24W5gGUvkVSoJlCq RIdg== X-Gm-Message-State: ABy/qLa/jBDKJHsM1SDFbnqS3cuVvgx/qs3bDHTUsQVgBmp9JEcEwiPx qL8LyaVkjN1/6/xfChBMjNqHSfna1ccHj/XxUGw= X-Google-Smtp-Source: APBJJlFPrxL9JHH4/NMiL06/Gk8CRGB5aCYg0UkggLByHahv5xrzg8gUPVuEBV/9UwB83rouQ5kWd4XmVY5elb7noZE= X-Received: by 2002:a05:6102:4191:b0:445:1f4e:28ad with SMTP id cd17-20020a056102419100b004451f4e28admr3361261vsb.7.1689589852769; Mon, 17 Jul 2023 03:30:52 -0700 (PDT) MIME-Version: 1.0 References: <20230717095259.326307-1-lehua.ding@rivai.ai> In-Reply-To: <20230717095259.326307-1-lehua.ding@rivai.ai> From: Kito Cheng Date: Mon, 17 Jul 2023 18:30:41 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Ensure all implied extensions are included[PR110696] To: Lehua Ding Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM, thanks for the patch :) On Mon, Jul 17, 2023 at 5:53=E2=80=AFPM Lehua Ding wr= ote: > > Hi, > > This patch fix target/PR110696, recursively add all implied extensions. > > Best, > Lehua > > PR target/110696 > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc (riscv_subset_list::handle_= implied_ext): recur add all implied extensions. > (riscv_subset_list::check_implied_ext): Add new method. > (riscv_subset_list::parse): Call checker check_implied_ext. > * config/riscv/riscv-subset.h: Add new method. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/attribute-20.c: New test. > * gcc.target/riscv/pr110696.c: New test. > > --- > gcc/common/config/riscv/riscv-common.cc | 33 +++++++++++++++++-- > gcc/config/riscv/riscv-subset.h | 3 +- > gcc/testsuite/gcc.target/riscv/attribute-20.c | 7 ++++ > gcc/testsuite/gcc.target/riscv/pr110696.c | 7 ++++ > 4 files changed, 46 insertions(+), 4 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-20.c > create mode 100644 gcc/testsuite/gcc.target/riscv/pr110696.c > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/= riscv/riscv-common.cc > index 28c8f0c1489..19075c0b241 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -949,14 +949,14 @@ riscv_subset_list::parse_std_ext (const char *p) > > /* Check any implied extensions for EXT. */ > void > -riscv_subset_list::handle_implied_ext (riscv_subset_t *ext) > +riscv_subset_list::handle_implied_ext (const char *ext) > { > const riscv_implied_info_t *implied_info; > for (implied_info =3D &riscv_implied_info[0]; > implied_info->ext; > ++implied_info) > { > - if (strcmp (ext->name.c_str (), implied_info->ext) !=3D 0) > + if (strcmp (ext, implied_info->ext) !=3D 0) > continue; > > /* Skip if implied extension already present. */ > @@ -966,6 +966,9 @@ riscv_subset_list::handle_implied_ext (riscv_subset_t= *ext) > /* Version of implied extension will get from current ISA spec > version. */ > add (implied_info->implied_ext, true); > + > + /* Recursively add implied extension by implied_info->implied_ext.= */ > + handle_implied_ext (implied_info->implied_ext); > } > > /* For RISC-V ISA version 2.2 or earlier version, zicsr and zifence is > @@ -980,6 +983,27 @@ riscv_subset_list::handle_implied_ext (riscv_subset_= t *ext) > } > } > > +/* Check that all implied extensions are included. */ > +bool > +riscv_subset_list::check_implied_ext () > +{ > + riscv_subset_t *itr; > + for (itr =3D m_head; itr !=3D NULL; itr =3D itr->next) > + { > + const riscv_implied_info_t *implied_info; > + for (implied_info =3D &riscv_implied_info[0]; implied_info->ext; > + ++implied_info) > + { > + if (strcmp (itr->name.c_str(), implied_info->ext) !=3D 0) > + continue; > + > + if (!lookup (implied_info->implied_ext)) > + return false; > + } > + } > + return true; > +} > + > /* Check any combine extensions for EXT. */ > void > riscv_subset_list::handle_combine_ext () > @@ -1194,9 +1218,12 @@ riscv_subset_list::parse (const char *arch, locati= on_t loc) > > for (itr =3D subset_list->m_head; itr !=3D NULL; itr =3D itr->next) > { > - subset_list->handle_implied_ext (itr); > + subset_list->handle_implied_ext (itr->name.c_str ()); > } > > + /* Make sure all implied extensions are included. */ > + gcc_assert (subset_list->check_implied_ext ()); > + > subset_list->handle_combine_ext (); > > if (subset_list->lookup ("zfinx") && subset_list->lookup ("f")) > diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-sub= set.h > index 92e4fb31692..84a7a82db63 100644 > --- a/gcc/config/riscv/riscv-subset.h > +++ b/gcc/config/riscv/riscv-subset.h > @@ -67,7 +67,8 @@ private: > const char *parse_multiletter_ext (const char *, const char *, > const char *); > > - void handle_implied_ext (riscv_subset_t *); > + void handle_implied_ext (const char *); > + bool check_implied_ext (); > void handle_combine_ext (); > > public: > diff --git a/gcc/testsuite/gcc.target/riscv/attribute-20.c b/gcc/testsuit= e/gcc.target/riscv/attribute-20.c > new file mode 100644 > index 00000000000..f7d0b29b71c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/attribute-20.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvl65536b -mabi=3Dlp64d" } */ > +int foo() > +{ > +} > + > +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2= p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f= 1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zv= l32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b= 1p0\"" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gc= c.target/riscv/pr110696.c > new file mode 100644 > index 00000000000..a630f04e74f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvl4096b -mabi=3Dlp64d" } */ > +int foo() > +{ > +} > + > +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2= p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f= 1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl40= 96b1p0_zvl512b1p0_zvl64b1p0\"" } } */ > -- > 2.36.3 >