From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa29.google.com (mail-vk1-xa29.google.com [IPv6:2607:f8b0:4864:20::a29]) by sourceware.org (Postfix) with ESMTPS id 3613A3858CDA for ; Fri, 12 May 2023 02:24:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3613A3858CDA Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa29.google.com with SMTP id 71dfb90a1353d-4501f454581so4437075e0c.3 for ; Thu, 11 May 2023 19:24:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683858239; x=1686450239; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=VMG5SadzOkjSluWBSxClZh9U9nn8B5RF8U5psv3Pb3o=; b=hwyy02xfJIcxAzTrqoKPyf5Ds8LNz6DEQrkM8LrpTkCj9Mw/3gRZ+AWHSATqT2Ba7x 5/aBysaCaLshsvKtVkv/qXIl8yWVQss5eeahSX6drxy6eD3BS/nEyQQ8sE1XqUADWTts faCbWZfubwsKkDCUTwCEhrBBj6Cnj2f+j8qzyfF7AdySEZXnzV7aqQTJrs5ATTcyo+ol 8L5oOHiIGo5v4vgYPYUcXesPf5oOOmpPRzJyk7Hh5oxKLf1IepZ+4fU7s9hcdJkRLsj/ vJDTj9wZ+FpTIkUjv3Xxbjez7xKqY1MUmWVaqsPA7CkqC0vztUeUhIoKaX79GciM5wy+ 3JWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683858239; x=1686450239; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=VMG5SadzOkjSluWBSxClZh9U9nn8B5RF8U5psv3Pb3o=; b=XBBh3wnqPMLyqUAwisQDrzz6w1lPGc8TVWQLe518Gd7R06nT7W01VX3TZF8n08iadg DH040O6M8qIm4IXSoXb5hsaN50LjaZz6rOciBFthe/bezmB7uuC3TMNC1bfKFf5+Pm3x qwB9Dg3UFjHnuFbu1+YcHrMEaZmUbFqOzTN3eQy1rIU+GhTNTPWmrewiDCqHLFhL7OQm U03uPIDibBs67xZU+H6WudxShvMs1uCEG/rQKfpy9ITHGUNefLqGply+IOyE/QjmKPQ6 nOAWimDE5Lohqbko7W1pZctzxzB2XRb4bcxBBVXOooYJ8tMlsTHykgCXRJ/My9jy6HHR 9mCA== X-Gm-Message-State: AC+VfDwtEu+gVLzaTHKyST09ikoDsfdfZevvgG0kfuYpSigXeix2w74l rvbiTl4X6g7XmU8h0DSZHxNMLeStwiUbaZMIuZI= X-Google-Smtp-Source: ACHHUZ7Gbq+ajlVx8Zu1XTAMAOKodl9Rq+J2qYe54uAWAXLo9LGccbl3l1kXcRq42NOT/rGAdFplwCVAx6EE+0UTk8w= X-Received: by 2002:a1f:3dc1:0:b0:453:753f:ef2e with SMTP id k184-20020a1f3dc1000000b00453753fef2emr2391601vka.8.1683858238744; Thu, 11 May 2023 19:23:58 -0700 (PDT) MIME-Version: 1.0 References: <20230512013112.276462-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230512013112.276462-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Fri, 12 May 2023 10:23:47 +0800 Message-ID: Subject: Re: [PATCH V2] RISC-V: Add basic vec_init for VLS RVV auto-vectorization To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > This patch makes vec_init support common init vector handling (using vslide1down to insert element) > which can handle any cases of initialization vec but it's not optimal for cases. > > And support Case 1 optimizaiton: > https://godbolt.org/z/Yb9PK9jsz Don't use godbolt link in comment, because they are not permanently preserved on the server, also the reference is not fixed since LLVM trunk could improve. > LLVM codegen: > https://godbolt.org/z/xsnavvWqx > > ... > vslide1down.vx (x128 times) > ... Drop LLVM codegen here, again, it might improve, healthy competition is good, but I would like to avoid disparaging other compilers in comments. :) > --- > gcc/config/riscv/autovec.md | 16 ++ > gcc/config/riscv/riscv-protos.h | 1 + > gcc/config/riscv/riscv-v.cc | 127 +++++++++++ > gcc/config/riscv/vector-iterators.md | 9 + > .../gcc.target/riscv/rvv/autovec/insert-1.c | 41 ++++ > .../gcc.target/riscv/rvv/autovec/insert-2.c | 41 ++++ > .../gcc.target/riscv/rvv/autovec/insert-3.c | 41 ++++ > .../riscv/rvv/autovec/insert_run-1.c | 46 ++++ > .../riscv/rvv/autovec/insert_run-2.c | 46 ++++ > .../gcc.target/riscv/rvv/autovec/repeat-1.c | 75 +++++++ > .../gcc.target/riscv/rvv/autovec/repeat-2.c | 61 ++++++ > .../gcc.target/riscv/rvv/autovec/repeat-3.c | 53 +++++ > .../gcc.target/riscv/rvv/autovec/repeat-4.c | 39 ++++ > .../gcc.target/riscv/rvv/autovec/repeat-5.c | 74 +++++++ > .../gcc.target/riscv/rvv/autovec/repeat-6.c | 78 +++++++ > .../riscv/rvv/autovec/repeat_run-1.c | 125 +++++++++++ > .../riscv/rvv/autovec/repeat_run-2.c | 145 +++++++++++++ > .../riscv/rvv/autovec/repeat_run-3.c | 203 ++++++++++++++++++ > .../riscv/rvv/autovec/repeat_run-4.c | 77 +++++++ > .../riscv/rvv/autovec/repeat_run-5.c | 124 +++++++++++ > .../riscv/rvv/autovec/repeat_run-6.c | 122 +++++++++++ > 21 files changed, 1544 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/insert-1.c Could you reorg the autovec folder to separate vls-vlmax and vla stuffs? > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/insert-2.c ... > +/* Initialize register TARGET from the elements in PARALLEL rtx VALS. */ > + > +void > +expand_vec_init (rtx target, rtx vals) > +{ > + machine_mode mode = GET_MODE (target); I would like to add some assertion here to ensure only VLS mode here.