From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x82f.google.com (mail-qt1-x82f.google.com [IPv6:2607:f8b0:4864:20::82f]) by sourceware.org (Postfix) with ESMTPS id 8F7293857009 for ; Sat, 10 Jun 2023 03:03:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8F7293857009 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qt1-x82f.google.com with SMTP id d75a77b69052e-3f9c7665317so20988941cf.3 for ; Fri, 09 Jun 2023 20:03:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686366206; x=1688958206; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=bdAmj5iXJSfwK5UPhdQ/rE8cbwMCLRinT9NF5G/ldEg=; b=nD0LjZ1Fw51PsLIrtxhpLU8eqc1Mu4bEgu0b/QY1xLvfnoUwL0mrYk/8ze4RBg1qkT awGoLLqPEEYdlOwF94jPl50dEas4FfOL4ZoxktFaWQQCiH+NKz/4x5RTvIvIxeyh7iWz rS5Zf/QsSvBHPa95AKZQeV3n2EEkwC8E9wLmWGVwTCE/x6kcRj0MmUBFqv51jUi+54pC Lzx08/7P8gAkPEJ/XO6Ol0r6RKUaTok0lPlGzlA3GRYxv5TmvrUvVui7hiF1aWhHv4XF 0Gl2uXY3sbLKey6Dw8g6j1M3/0hh9pJtBaYJww18zvl4Bs85Wp/CnljoHV5Gc46e+IHn WRYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686366206; x=1688958206; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bdAmj5iXJSfwK5UPhdQ/rE8cbwMCLRinT9NF5G/ldEg=; b=T7bko5KPePK8HzPjybH8xLHo2OK6jb6tFds362Mbm+kFYf9+4rwTYDQR1jwZVNVMkf A6G6twhlXMo1XRv9mtXY+UES1HeoZ0GFWyEDEr+iK7PXXYPaY7LAaNeqkVy0X8ow3m/L 3g2GDNx2iFdJfnHz6a3ibC9bpDN1CQbtqBRrUwuBPRxa1I5PzSv/MMHWmTp3meE/I220 ssZHaD0Ow3yS16tY8GwHOKTHw4yywBHgNbTD23wxbfdiO0CUCe6IKOGXehyEiXh3J9K0 agZBLSRmGyacYU+N+92rlwHGZYknJB7mCejqp36VHk8W9o8FxQ5mAGpfhdWm5rpx7VPO JW3Q== X-Gm-Message-State: AC+VfDwJ0lQbJPi+6E8BFvmcDFf1/Q/J2K+k2ez4/gTRXKqehXjkjwIC ohrUWiV1E3+ZsJpXHhRtQ1QeuB4e+Rh3dsWf59k= X-Google-Smtp-Source: ACHHUZ6jAeNokxOZw2Sfh/wwbzsDAGB+XopKQE7F3eW1wJwkMq+oZ40bCvzknRJndI0qf7fnX5MmPKff0446JjNhUXI= X-Received: by 2002:a05:6214:2524:b0:625:85f0:6187 with SMTP id gg4-20020a056214252400b0062585f06187mr4211957qvb.1.1686366205525; Fri, 09 Jun 2023 20:03:25 -0700 (PDT) MIME-Version: 1.0 References: <20230610003737.1679827-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230610003737.1679827-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Sat, 10 Jun 2023 11:03:14 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Enable select_vl for RVV auto-vectorization To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, palmer@rivosinc.com, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM, thanks for this!!!! On Sat, Jun 10, 2023 at 8:42=E2=80=AFAM wrote: > > From: Juzhe-Zhong > > Consider this following example: > void vec_add(int32_t *restrict c, int32_t *restrict a, int32_t *restrict = b, > int N) { > for (long i =3D 0; i < N; i++) { > c[i] =3D a[i] + b[i]; > } > } > > After this patch: > vec_add: > ble a3,zero,.L5 > .L3: > vsetvli a5,a3,e32,m1,ta,ma > vle32.v v2,0(a1) > vle32.v v1,0(a2) > vsetvli a6,zero,e32,m1,ta,ma =3D=3D=3D> redundant vsetvl. > slli a4,a5,2 > vadd.vv v1,v1,v2 > sub a3,a3,a5 > vsetvli zero,a5,e32,m1,ta,ma =3D=3D=3D> redundant vsetvl. > vse32.v v1,0(a0) > add a1,a1,a4 > add a2,a2,a4 > add a0,a0,a4 > bne a3,zero,.L3 > .L5: > ret > > We can get close-to-optimal codegen but with some redundant vsetvls. > This is not the big issue which will be easily addressed in RISC-V backen= d. > > I am going to add a standalone PASS "AVL propagation" (avlprop) to addres= se > such issue. > > gcc/ChangeLog: > > * config/riscv/autovec.md (select_vl): New pattern. > * config/riscv/riscv-protos.h (expand_select_vl): New function. > * config/riscv/riscv-v.cc (expand_select_vl): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: Adapt test. > * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: Ditto. > * gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: New test. > > --- > gcc/config/riscv/autovec.md | 14 ++++++++++ > gcc/config/riscv/riscv-protos.h | 1 + > gcc/config/riscv/riscv-v.cc | 12 +++++++++ > .../riscv/rvv/autovec/partial/select_vl-1.c | 26 +++++++++++++++++++ > .../riscv/rvv/autovec/ternop/ternop-2.c | 2 +- > .../riscv/rvv/autovec/ternop/ternop-5.c | 2 +- > 6 files changed, 55 insertions(+), 2 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/se= lect_vl-1.c > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index 9f4492db23c..b7070099f29 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -626,3 +626,17 @@ > } > [(set_attr "type" "vimuladd") > (set_attr "mode" "")]) > + > +;; =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > +;; =3D=3D SELECT_VL > +;; =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + > +(define_expand "select_vl" > + [(match_operand:P 0 "register_operand") > + (match_operand:P 1 "vector_length_operand") > + (match_operand:P 2 "")] > + "TARGET_VECTOR" > +{ > + riscv_vector::expand_select_vl (operands); > + DONE; > +}) > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-pro= tos.h > index 66c1f535d60..6db3a46c682 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -246,6 +246,7 @@ void expand_vec_series (rtx, rtx, rtx); > void expand_vec_init (rtx, rtx); > void expand_vcond (rtx *); > void expand_vec_perm (rtx, rtx, rtx, rtx); > +void expand_select_vl (rtx *); > /* Rounding mode bitfield for fixed point VXRM. */ > enum vxrm_field_enum > { > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index 477a22cd2b0..e1b85a5af91 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -2447,4 +2447,16 @@ expand_vec_perm_const (machine_mode vmode, machine= _mode op_mode, rtx target, > return ret; > } > > +/* Generate no side effects vsetvl to get the vector length. */ > +void > +expand_select_vl (rtx *ops) > +{ > + poly_int64 nunits =3D rtx_to_poly_int64 (ops[2]); > + /* We arbitrary picked QImode as inner scalar mode to get vector mode. > + since vsetvl only demand ratio. We let VSETVL PASS to optimize it. = */ > + scalar_int_mode mode =3D QImode; > + machine_mode rvv_mode =3D get_vector_mode (mode, nunits).require (); > + emit_insn (gen_no_side_effects_vsetvl_rtx (rvv_mode, ops[0], ops[1])); > +} > + > } // namespace riscv_vector > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl= -1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c > new file mode 100644 > index 00000000000..74bbf40ee9f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c > @@ -0,0 +1,26 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-march=3Drv32gcv -mabi=3Dilp32d --param risc= v-autovec-preference=3Dscalable -fno-vect-cost-model -fno-tree-loop-distrib= ute-patterns -fdump-tree-optimized-details" } */ > + > +#include > + > +#define TEST_TYPE(TYPE) = \ > + __attribute__ ((noipa)) void select_vl_##TYPE (TYPE *__restrict dst, = \ > + TYPE *__restrict a, int = n) \ > + { = \ > + for (int i =3D 0; i < n; i++) = \ > + dst[i] =3D a[i]; = \ > + } > + > +#define TEST_ALL() = \ > + TEST_TYPE (int8_t) = \ > + TEST_TYPE (uint8_t) = \ > + TEST_TYPE (int16_t) = \ > + TEST_TYPE (uint16_t) = \ > + TEST_TYPE (int32_t) = \ > + TEST_TYPE (uint32_t) = \ > + TEST_TYPE (int64_t) = \ > + TEST_TYPE (uint64_t) = \ > + TEST_TYPE (float) = \ > + TEST_TYPE (double) > + > +TEST_ALL () > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c > index 89eeaf6315f..e52e07ddd09 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-additional-options "-march=3Drv32gcv -mabi=3Dilp32d --param=3Dri= scv-autovec-preference=3Dscalable" } */ > +/* { dg-additional-options "-march=3Drv32gcv -mabi=3Dilp32d --param=3Dri= scv-autovec-preference=3Dscalable -fno-schedule-insns" } */ > > #include > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c > index a9a7198feb4..49c85efbf3a 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-additional-options "-march=3Drv32gcv -mabi=3Dilp32d --param=3Dri= scv-autovec-preference=3Dscalable" } */ > +/* { dg-additional-options "-march=3Drv32gcv -mabi=3Dilp32d --param=3Dri= scv-autovec-preference=3Dscalable -fno-schedule-insns" } */ > > #include > > -- > 2.36.3 >